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Merge branch 'regulator-5.0' into regulator-5.1 stpmic1 const/range

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This commit is contained in:
Mark Brown 2019-02-19 11:06:41 +00:00
commit 16646d8d3d
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GPG Key ID: 24D68B725D5487D0
13 changed files with 152 additions and 143 deletions
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12
drivers/regulator/axp20x-regulator.c
View File

@ -577,7 +577,7 @@ static const struct regulator_desc axp22x_regulators[] = {
AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT,
AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
@ -795,7 +795,7 @@ static const struct regulator_desc axp806_regulators[] = {
AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL,
AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
@ -821,7 +821,7 @@ static const struct regulator_desc axp806_regulators[] = {
AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL,
AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
@ -956,7 +956,7 @@ static const struct regulator_desc axp813_regulators[] = {
AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT,
AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
@ -966,7 +966,7 @@ static const struct regulator_desc axp813_regulators[] = {
AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT,
AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
@ -981,7 +981,7 @@ static const struct regulator_desc axp813_regulators[] = {
AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT,
AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
/* to do / check ... */
AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,

4
drivers/regulator/bcm590xx-regulator.c
View File

@ -242,8 +242,12 @@ static int bcm590xx_get_enable_register(int id)
case BCM590XX_REG_SDSR2:
reg = BCM590XX_SDSR2PMCTRL1;
break;
case BCM590XX_REG_VSR:
reg = BCM590XX_VSRPMCTRL1;
break;
case BCM590XX_REG_VBUS:
reg = BCM590XX_OTG_CTRL;
break;
}

12
drivers/regulator/core.c
View File

@ -1337,7 +1337,9 @@ static int set_machine_constraints(struct regulator_dev *rdev,
* We'll only apply the initial system load if an
* initial mode wasn't specified.
*/
regulator_lock(rdev);
drms_uA_update(rdev);
regulator_unlock(rdev);
}
if ((rdev->constraints->ramp_delay || rdev->constraints->ramp_disable)
@ -2046,15 +2048,7 @@ static void _regulator_put(struct regulator *regulator)
debugfs_remove_recursive(regulator->debugfs);
if (regulator->dev) {
int count = 0;
struct regulator *r;
list_for_each_entry(r, &rdev->consumer_list, list)
if (r->dev == regulator->dev)
count++;
if (count == 1)
device_link_remove(regulator->dev, &rdev->dev);
device_link_remove(regulator->dev, &rdev->dev);
/* remove any sysfs entries */
sysfs_remove_link(&rdev->dev.kobj, regulator->supply_name);

64
drivers/regulator/da9052-regulator.c
View File

@ -290,10 +290,10 @@ static const struct regulator_ops da9052_ldo_ops = {
.disable = regulator_disable_regmap,
};
#define DA9052_LDO(_id, step, min, max, sbits, ebits, abits) \
#define DA9052_LDO(_id, _name, step, min, max, sbits, ebits, abits) \
{\
.reg_desc = {\
.name = #_id,\
.name = #_name,\
.ops = &da9052_ldo_ops,\
.type = REGULATOR_VOLTAGE,\
.id = DA9052_ID_##_id,\
@ -310,10 +310,10 @@ static const struct regulator_ops da9052_ldo_ops = {
.activate_bit = (abits),\
}
#define DA9052_DCDC(_id, step, min, max, sbits, ebits, abits) \
#define DA9052_DCDC(_id, _name, step, min, max, sbits, ebits, abits) \
{\
.reg_desc = {\
.name = #_id,\
.name = #_name,\
.ops = &da9052_dcdc_ops,\
.type = REGULATOR_VOLTAGE,\
.id = DA9052_ID_##_id,\
@ -331,37 +331,37 @@ static const struct regulator_ops da9052_ldo_ops = {
}
static struct da9052_regulator_info da9052_regulator_info[] = {
DA9052_DCDC(BUCK1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
DA9052_DCDC(BUCK2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
DA9052_DCDC(BUCK3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
DA9052_DCDC(BUCK4, 50, 1800, 3600, 5, 6, 0),
DA9052_LDO(LDO1, 50, 600, 1800, 5, 6, 0),
DA9052_LDO(LDO2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
DA9052_LDO(LDO3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
DA9052_LDO(LDO4, 25, 1725, 3300, 6, 6, 0),
DA9052_LDO(LDO5, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO6, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO7, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO8, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO9, 50, 1250, 3650, 6, 6, 0),
DA9052_LDO(LDO10, 50, 1200, 3600, 6, 6, 0),
DA9052_DCDC(BUCK1, buck1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
DA9052_DCDC(BUCK2, buck2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
DA9052_DCDC(BUCK3, buck3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
DA9052_DCDC(BUCK4, buck4, 50, 1800, 3600, 5, 6, 0),
DA9052_LDO(LDO1, ldo1, 50, 600, 1800, 5, 6, 0),
DA9052_LDO(LDO2, ldo2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
DA9052_LDO(LDO3, ldo3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
DA9052_LDO(LDO4, ldo4, 25, 1725, 3300, 6, 6, 0),
DA9052_LDO(LDO5, ldo5, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO6, ldo6, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO7, ldo7, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO8, ldo8, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO9, ldo9, 50, 1250, 3650, 6, 6, 0),
DA9052_LDO(LDO10, ldo10, 50, 1200, 3600, 6, 6, 0),
};
static struct da9052_regulator_info da9053_regulator_info[] = {
DA9052_DCDC(BUCK1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
DA9052_DCDC(BUCK2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
DA9052_DCDC(BUCK3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
DA9052_DCDC(BUCK4, 25, 950, 2525, 6, 6, 0),
DA9052_LDO(LDO1, 50, 600, 1800, 5, 6, 0),
DA9052_LDO(LDO2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
DA9052_LDO(LDO3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
DA9052_LDO(LDO4, 25, 1725, 3300, 6, 6, 0),
DA9052_LDO(LDO5, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO6, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO7, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO8, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO9, 50, 1250, 3650, 6, 6, 0),
DA9052_LDO(LDO10, 50, 1200, 3600, 6, 6, 0),
DA9052_DCDC(BUCK1, buck1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
DA9052_DCDC(BUCK2, buck2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
DA9052_DCDC(BUCK3, buck3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
DA9052_DCDC(BUCK4, buck4, 25, 950, 2525, 6, 6, 0),
DA9052_LDO(LDO1, ldo1, 50, 600, 1800, 5, 6, 0),
DA9052_LDO(LDO2, ldo2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
DA9052_LDO(LDO3, ldo3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
DA9052_LDO(LDO4, ldo4, 25, 1725, 3300, 6, 6, 0),
DA9052_LDO(LDO5, ldo5, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO6, ldo6, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO7, ldo7, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO8, ldo8, 50, 1200, 3600, 6, 6, 0),
DA9052_LDO(LDO9, ldo9, 50, 1250, 3650, 6, 6, 0),
DA9052_LDO(LDO10, ldo10, 50, 1200, 3600, 6, 6, 0),
};
static inline struct da9052_regulator_info *find_regulator_info(u8 chip_id,

4
drivers/regulator/lochnagar-regulator.c
View File

@ -194,7 +194,7 @@ static const struct regulator_desc lochnagar_regulators[] = {
.name = "VDDCORE",
.supply_name = "SYSVDD",
.type = REGULATOR_VOLTAGE,
.n_voltages = 57,
.n_voltages = 66,
.ops = &lochnagar_vddcore_ops,
.id = LOCHNAGAR_VDDCORE,
@ -226,7 +226,7 @@ static const struct of_device_id lochnagar_of_match[] = {
},
{
.compatible = "cirrus,lochnagar2-mic2vdd",
.data = &lochnagar_regulators[LOCHNAGAR_MIC1VDD],
.data = &lochnagar_regulators[LOCHNAGAR_MIC2VDD],
},
{
.compatible = "cirrus,lochnagar2-vddcore",

10
drivers/regulator/max77620-regulator.c
View File

@ -1,7 +1,7 @@
/*
* Maxim MAX77620 Regulator driver
*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
* Laxman Dewangan <ldewangan@nvidia.com>
@ -803,6 +803,14 @@ static int max77620_regulator_probe(struct platform_device *pdev)
rdesc = &rinfo[id].desc;
pmic->rinfo[id] = &max77620_regs_info[id];
pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
pmic->reg_pdata[id].active_fps_src = -1;
pmic->reg_pdata[id].active_fps_pd_slot = -1;
pmic->reg_pdata[id].active_fps_pu_slot = -1;
pmic->reg_pdata[id].suspend_fps_src = -1;
pmic->reg_pdata[id].suspend_fps_pd_slot = -1;
pmic->reg_pdata[id].suspend_fps_pu_slot = -1;
pmic->reg_pdata[id].power_ok = -1;
pmic->reg_pdata[id].ramp_rate_setting = -1;
ret = max77620_read_slew_rate(pmic, id);
if (ret < 0)

76
drivers/regulator/mc13783-regulator.c
View File

@ -228,67 +228,67 @@ static const unsigned int mc13783_pwgtdrv_val[] = {
static struct regulator_ops mc13783_gpo_regulator_ops;
#define MC13783_DEFINE(prefix, name, reg, vsel_reg, voltages) \
MC13xxx_DEFINE(MC13783_REG_, name, reg, vsel_reg, voltages, \
#define MC13783_DEFINE(prefix, name, node, reg, vsel_reg, voltages) \
MC13xxx_DEFINE(MC13783_REG_, name, node, reg, vsel_reg, voltages, \
mc13xxx_regulator_ops)
#define MC13783_FIXED_DEFINE(prefix, name, reg, voltages) \
MC13xxx_FIXED_DEFINE(MC13783_REG_, name, reg, voltages, \
#define MC13783_FIXED_DEFINE(prefix, name, node, reg, voltages) \
MC13xxx_FIXED_DEFINE(MC13783_REG_, name, node, reg, voltages, \
mc13xxx_fixed_regulator_ops)
#define MC13783_GPO_DEFINE(prefix, name, reg, voltages) \
MC13xxx_GPO_DEFINE(MC13783_REG_, name, reg, voltages, \
#define MC13783_GPO_DEFINE(prefix, name, node, reg, voltages) \
MC13xxx_GPO_DEFINE(MC13783_REG_, name, node, reg, voltages, \
mc13783_gpo_regulator_ops)
#define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \
MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
#define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \
MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
#define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \
MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
#define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages) \
MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
static struct mc13xxx_regulator mc13783_regulators[] = {
MC13783_DEFINE_SW(SW1A, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
MC13783_DEFINE_SW(SW1B, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
MC13783_DEFINE_SW(SW2A, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
MC13783_DEFINE_SW(SW2B, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
MC13783_DEFINE_SW(SW1A, sw1a, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
MC13783_DEFINE_SW(SW1B, sw1b, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
MC13783_DEFINE_SW(SW2A, sw2a, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
MC13783_DEFINE_SW(SW2B, sw2b, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
MC13783_DEFINE_SW(SW3, sw3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0,
MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val),
MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val),
MC13783_DEFINE_REGU(VIOLO, violo, REGULATORMODE0, REGULATORSETTING0,
mc13783_violo_val),
MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0,
MC13783_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
mc13783_vdig_val),
MC13783_DEFINE_REGU(VGEN, REGULATORMODE0, REGULATORSETTING0,
MC13783_DEFINE_REGU(VGEN, vgen, REGULATORMODE0, REGULATORSETTING0,
mc13783_vgen_val),
MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0, REGULATORSETTING0,
MC13783_DEFINE_REGU(VRFDIG, vrfdig, REGULATORMODE0, REGULATORSETTING0,
mc13783_vrfdig_val),
MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0, REGULATORSETTING0,
MC13783_DEFINE_REGU(VRFREF, vrfref, REGULATORMODE0, REGULATORSETTING0,
mc13783_vrfref_val),
MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0, REGULATORSETTING0,
MC13783_DEFINE_REGU(VRFCP, vrfcp, REGULATORMODE0, REGULATORSETTING0,
mc13783_vrfcp_val),
MC13783_DEFINE_REGU(VSIM, REGULATORMODE1, REGULATORSETTING0,
MC13783_DEFINE_REGU(VSIM, vsim, REGULATORMODE1, REGULATORSETTING0,
mc13783_vsim_val),
MC13783_DEFINE_REGU(VESIM, REGULATORMODE1, REGULATORSETTING0,
MC13783_DEFINE_REGU(VESIM, vesim, REGULATORMODE1, REGULATORSETTING0,
mc13783_vesim_val),
MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0,
MC13783_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
mc13783_vcam_val),
MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1,
MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val),
MC13783_DEFINE_REGU(VVIB, vvib, REGULATORMODE1, REGULATORSETTING1,
mc13783_vvib_val),
MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1,
MC13783_DEFINE_REGU(VRF1, vrf1, REGULATORMODE1, REGULATORSETTING1,
mc13783_vrf_val),
MC13783_DEFINE_REGU(VRF2, REGULATORMODE1, REGULATORSETTING1,
MC13783_DEFINE_REGU(VRF2, vrf2, REGULATORMODE1, REGULATORSETTING1,
mc13783_vrf_val),
MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1, REGULATORSETTING1,
MC13783_DEFINE_REGU(VMMC1, vmmc1, REGULATORMODE1, REGULATORSETTING1,
mc13783_vmmc_val),
MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1,
MC13783_DEFINE_REGU(VMMC2, vmmc2, REGULATORMODE1, REGULATORSETTING1,
mc13783_vmmc_val),
MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),
MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val),
MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val),
MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val),
MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val),
};
static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,

64
drivers/regulator/mc13892-regulator.c
View File

@ -246,57 +246,57 @@ static struct regulator_ops mc13892_gpo_regulator_ops;
static struct regulator_ops mc13892_sw_regulator_ops;
#define MC13892_FIXED_DEFINE(name, reg, voltages) \
MC13xxx_FIXED_DEFINE(MC13892_, name, reg, voltages, \
#define MC13892_FIXED_DEFINE(name, node, reg, voltages) \
MC13xxx_FIXED_DEFINE(MC13892_, name, node, reg, voltages, \
mc13xxx_fixed_regulator_ops)
#define MC13892_GPO_DEFINE(name, reg, voltages) \
MC13xxx_GPO_DEFINE(MC13892_, name, reg, voltages, \
#define MC13892_GPO_DEFINE(name, node, reg, voltages) \
MC13xxx_GPO_DEFINE(MC13892_, name, node, reg, voltages, \
mc13892_gpo_regulator_ops)
#define MC13892_SW_DEFINE(name, reg, vsel_reg, voltages) \
MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
#define MC13892_SW_DEFINE(name, node, reg, vsel_reg, voltages) \
MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
mc13892_sw_regulator_ops)
#define MC13892_DEFINE_REGU(name, reg, vsel_reg, voltages) \
MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
#define MC13892_DEFINE_REGU(name, node, reg, vsel_reg, voltages) \
MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
mc13xxx_regulator_ops)
static struct mc13xxx_regulator mc13892_regulators[] = {
MC13892_DEFINE_REGU(VCOINCELL, POWERCTL0, POWERCTL0, mc13892_vcoincell),
MC13892_SW_DEFINE(SW1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
MC13892_SW_DEFINE(SW2, SWITCHERS1, SWITCHERS1, mc13892_sw),
MC13892_SW_DEFINE(SW3, SWITCHERS2, SWITCHERS2, mc13892_sw),
MC13892_SW_DEFINE(SW4, SWITCHERS3, SWITCHERS3, mc13892_sw),
MC13892_FIXED_DEFINE(SWBST, SWITCHERS5, mc13892_swbst),
MC13892_FIXED_DEFINE(VIOHI, REGULATORMODE0, mc13892_viohi),
MC13892_DEFINE_REGU(VPLL, REGULATORMODE0, REGULATORSETTING0,
MC13892_DEFINE_REGU(VCOINCELL, vcoincell, POWERCTL0, POWERCTL0, mc13892_vcoincell),
MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
MC13892_SW_DEFINE(SW2, sw2, SWITCHERS1, SWITCHERS1, mc13892_sw),
MC13892_SW_DEFINE(SW3, sw3, SWITCHERS2, SWITCHERS2, mc13892_sw),
MC13892_SW_DEFINE(SW4, sw4, SWITCHERS3, SWITCHERS3, mc13892_sw),
MC13892_FIXED_DEFINE(SWBST, swbst, SWITCHERS5, mc13892_swbst),
MC13892_FIXED_DEFINE(VIOHI, viohi, REGULATORMODE0, mc13892_viohi),
MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
mc13892_vpll),
MC13892_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0,
MC13892_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
mc13892_vdig),
MC13892_DEFINE_REGU(VSD, REGULATORMODE1, REGULATORSETTING1,
MC13892_DEFINE_REGU(VSD, vsd, REGULATORMODE1, REGULATORSETTING1,
mc13892_vsd),
MC13892_DEFINE_REGU(VUSB2, REGULATORMODE0, REGULATORSETTING0,
MC13892_DEFINE_REGU(VUSB2, vusb2, REGULATORMODE0, REGULATORSETTING0,
mc13892_vusb2),
MC13892_DEFINE_REGU(VVIDEO, REGULATORMODE1, REGULATORSETTING1,
MC13892_DEFINE_REGU(VVIDEO, vvideo, REGULATORMODE1, REGULATORSETTING1,
mc13892_vvideo),
MC13892_DEFINE_REGU(VAUDIO, REGULATORMODE1, REGULATORSETTING1,
MC13892_DEFINE_REGU(VAUDIO, vaudio, REGULATORMODE1, REGULATORSETTING1,
mc13892_vaudio),
MC13892_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0,
MC13892_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
mc13892_vcam),
MC13892_DEFINE_REGU(VGEN1, REGULATORMODE0, REGULATORSETTING0,
MC13892_DEFINE_REGU(VGEN1, vgen1, REGULATORMODE0, REGULATORSETTING0,
mc13892_vgen1),
MC13892_DEFINE_REGU(VGEN2, REGULATORMODE0, REGULATORSETTING0,
MC13892_DEFINE_REGU(VGEN2, vgen2, REGULATORMODE0, REGULATORSETTING0,
mc13892_vgen2),
MC13892_DEFINE_REGU(VGEN3, REGULATORMODE1, REGULATORSETTING0,
MC13892_DEFINE_REGU(VGEN3, vgen3, REGULATORMODE1, REGULATORSETTING0,
mc13892_vgen3),
MC13892_FIXED_DEFINE(VUSB, USB1, mc13892_vusb),
MC13892_GPO_DEFINE(GPO1, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(GPO2, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(GPO3, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(GPO4, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(PWGT1SPI, POWERMISC, mc13892_pwgtdrv),
MC13892_GPO_DEFINE(PWGT2SPI, POWERMISC, mc13892_pwgtdrv),
MC13892_FIXED_DEFINE(VUSB, vusb, USB1, mc13892_vusb),
MC13892_GPO_DEFINE(GPO1, gpo1, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(GPO2, gpo2, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(GPO3, gpo3, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(GPO4, gpo4, POWERMISC, mc13892_gpo),
MC13892_GPO_DEFINE(PWGT1SPI, pwgt1spi, POWERMISC, mc13892_pwgtdrv),
MC13892_GPO_DEFINE(PWGT2SPI, pwgt2spi, POWERMISC, mc13892_pwgtdrv),
};
static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,

20
drivers/regulator/mc13xxx.h
View File

@ -56,10 +56,10 @@ static inline struct mc13xxx_regulator_init_data *mc13xxx_parse_regulators_dt(
extern struct regulator_ops mc13xxx_regulator_ops;
extern struct regulator_ops mc13xxx_fixed_regulator_ops;
#define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \
#define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \
[prefix ## _name] = { \
.desc = { \
.name = #_name, \
.name = #_node, \
.n_voltages = ARRAY_SIZE(_voltages), \
.volt_table = _voltages, \
.ops = &_ops, \
@ -74,10 +74,10 @@ extern struct regulator_ops mc13xxx_fixed_regulator_ops;
.vsel_mask = prefix ## _vsel_reg ## _ ## _name ## VSEL_M,\
}
#define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \
#define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \
[prefix ## _name] = { \
.desc = { \
.name = #_name, \
.name = #_node, \
.n_voltages = ARRAY_SIZE(_voltages), \
.volt_table = _voltages, \
.ops = &_ops, \
@ -89,10 +89,10 @@ extern struct regulator_ops mc13xxx_fixed_regulator_ops;
.enable_bit = prefix ## _reg ## _ ## _name ## EN, \
}
#define MC13xxx_GPO_DEFINE(prefix, _name, _reg, _voltages, _ops) \
#define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \
[prefix ## _name] = { \
.desc = { \
.name = #_name, \
.name = #_node, \
.n_voltages = ARRAY_SIZE(_voltages), \
.volt_table = _voltages, \
.ops = &_ops, \
@ -104,9 +104,9 @@ extern struct regulator_ops mc13xxx_fixed_regulator_ops;
.enable_bit = prefix ## _reg ## _ ## _name ## EN, \
}
#define MC13xxx_DEFINE_SW(_name, _reg, _vsel_reg, _voltages, ops) \
MC13xxx_DEFINE(SW, _name, _reg, _vsel_reg, _voltages, ops)
#define MC13xxx_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages, ops) \
MC13xxx_DEFINE(REGU, _name, _reg, _vsel_reg, _voltages, ops)
#define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \
MC13xxx_DEFINE(SW, _name, _node, _reg, _vsel_reg, _voltages, ops)
#define MC13xxx_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages, ops) \
MC13xxx_DEFINE(REGU, _name, _node, _reg, _vsel_reg, _voltages, ops)
#endif

10
drivers/regulator/s2mpa01.c
View File

@ -298,13 +298,13 @@ static const struct regulator_desc regulators[] = {
regulator_desc_ldo(2, STEP_50_MV),
regulator_desc_ldo(3, STEP_50_MV),
regulator_desc_ldo(4, STEP_50_MV),
regulator_desc_ldo(5, STEP_50_MV),
regulator_desc_ldo(5, STEP_25_MV),
regulator_desc_ldo(6, STEP_25_MV),
regulator_desc_ldo(7, STEP_50_MV),
regulator_desc_ldo(8, STEP_50_MV),
regulator_desc_ldo(9, STEP_50_MV),
regulator_desc_ldo(10, STEP_50_MV),
regulator_desc_ldo(11, STEP_25_MV),
regulator_desc_ldo(11, STEP_50_MV),
regulator_desc_ldo(12, STEP_50_MV),
regulator_desc_ldo(13, STEP_50_MV),
regulator_desc_ldo(14, STEP_50_MV),
@ -315,11 +315,11 @@ static const struct regulator_desc regulators[] = {
regulator_desc_ldo(19, STEP_50_MV),
regulator_desc_ldo(20, STEP_50_MV),
regulator_desc_ldo(21, STEP_50_MV),
regulator_desc_ldo(22, STEP_25_MV),
regulator_desc_ldo(23, STEP_25_MV),
regulator_desc_ldo(22, STEP_50_MV),
regulator_desc_ldo(23, STEP_50_MV),
regulator_desc_ldo(24, STEP_50_MV),
regulator_desc_ldo(25, STEP_50_MV),
regulator_desc_ldo(26, STEP_50_MV),
regulator_desc_ldo(26, STEP_25_MV),
regulator_desc_buck1_4(1),
regulator_desc_buck1_4(2),
regulator_desc_buck1_4(3),

6
drivers/regulator/s2mps11.c
View File

@ -362,7 +362,7 @@ static const struct regulator_desc s2mps11_regulators[] = {
regulator_desc_s2mps11_ldo(32, STEP_50_MV),
regulator_desc_s2mps11_ldo(33, STEP_50_MV),
regulator_desc_s2mps11_ldo(34, STEP_50_MV),
regulator_desc_s2mps11_ldo(35, STEP_50_MV),
regulator_desc_s2mps11_ldo(35, STEP_25_MV),
regulator_desc_s2mps11_ldo(36, STEP_50_MV),
regulator_desc_s2mps11_ldo(37, STEP_50_MV),
regulator_desc_s2mps11_ldo(38, STEP_50_MV),
@ -372,8 +372,8 @@ static const struct regulator_desc s2mps11_regulators[] = {
regulator_desc_s2mps11_buck1_4(4),
regulator_desc_s2mps11_buck5,
regulator_desc_s2mps11_buck67810(6, MIN_600_MV, STEP_6_25_MV),
regulator_desc_s2mps11_buck67810(7, MIN_600_MV, STEP_6_25_MV),
regulator_desc_s2mps11_buck67810(8, MIN_600_MV, STEP_6_25_MV),
regulator_desc_s2mps11_buck67810(7, MIN_600_MV, STEP_12_5_MV),
regulator_desc_s2mps11_buck67810(8, MIN_600_MV, STEP_12_5_MV),
regulator_desc_s2mps11_buck9,
regulator_desc_s2mps11_buck67810(10, MIN_750_MV, STEP_12_5_MV),
};

5
drivers/regulator/stpmic1_regulator.c
View File

@ -56,8 +56,9 @@ enum {
#define PMIC_ENABLE_TIME_US 2200
static const struct regulator_linear_range buck1_ranges[] = {
REGULATOR_LINEAR_RANGE(600000, 0, 30, 25000),
REGULATOR_LINEAR_RANGE(1350000, 31, 63, 0),
REGULATOR_LINEAR_RANGE(725000, 0, 4, 0),
REGULATOR_LINEAR_RANGE(725000, 5, 36, 25000),
REGULATOR_LINEAR_RANGE(1500000, 37, 63, 0),
};
static const struct regulator_linear_range buck2_ranges[] = {

8
drivers/regulator/uniphier-regulator.c
View File

@ -32,7 +32,7 @@ struct uniphier_regulator_priv {
const struct uniphier_regulator_soc_data *data;
};
static struct regulator_ops uniphier_regulator_ops = {
static const struct regulator_ops uniphier_regulator_ops = {
.enable = regulator_enable_regmap,
.disable = regulator_disable_regmap,
.is_enabled = regulator_is_enabled_regmap,
@ -87,8 +87,10 @@ static int uniphier_regulator_probe(struct platform_device *pdev)
}
regmap = devm_regmap_init_mmio(dev, base, priv->data->regconf);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto out_rst_assert;
}
config.dev = dev;
config.driver_data = priv;