mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 19:56:49 +07:00
x86: clean up cpu capabilities accesses, amd.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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9716951efd
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16282a8e25
@ -68,7 +68,7 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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if (cpuid_eax(0x80000000) >= 0x80000007) {
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c->x86_power = cpuid_edx(0x80000007);
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if (c->x86_power & (1<<8))
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set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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}
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}
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@ -105,9 +105,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_bit(0*32+31, c->x86_capability);
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clear_cpu_cap(c, 0*32+31);
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r = get_model_name(c);
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@ -131,8 +131,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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if (c->x86_model < 6) {
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/* Based on AMD doc 20734R - June 2000 */
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if (c->x86_model == 0) {
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clear_bit(X86_FEATURE_APIC, c->x86_capability);
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set_bit(X86_FEATURE_PGE, c->x86_capability);
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clear_cpu_cap(c, X86_FEATURE_APIC);
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set_cpu_cap(c, X86_FEATURE_PGE);
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}
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break;
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}
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@ -208,7 +208,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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/* Set MTRR capability flag if appropriate */
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if (c->x86_model == 13 || c->x86_model == 9 ||
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(c->x86_model == 8 && c->x86_mask >= 8))
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set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_K6_MTRR);
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break;
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}
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@ -231,7 +231,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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rdmsr(MSR_K7_HWCR, l, h);
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l &= ~0x00008000;
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wrmsr(MSR_K7_HWCR, l, h);
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set_bit(X86_FEATURE_XMM, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_XMM);
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}
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}
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@ -256,14 +256,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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/* Use K8 tuning for Fam10h and Fam11h */
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case 0x10:
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case 0x11:
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set_bit(X86_FEATURE_K8, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_K8);
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break;
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case 6:
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set_bit(X86_FEATURE_K7, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_K7);
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break;
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}
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if (c->x86 >= 6)
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set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
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display_cacheinfo(c);
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@ -304,10 +304,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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/* K6s reports MCEs but don't actually have all the MSRs */
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if (c->x86 < 6)
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clear_bit(X86_FEATURE_MCE, c->x86_capability);
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clear_cpu_cap(c, X86_FEATURE_MCE);
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if (cpu_has_xmm2)
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set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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}
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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