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drm/radeon/kms: fix pal tv-out support on legacy IGP chips

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Based on ddx patch by Andrzej Hajda.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher 2010-03-10 18:33:03 -05:00 committed by Dave Airlie
parent 267364ac17
commit 15f7207761
1 changed files with 24 additions and 5 deletions
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29
drivers/gpu/drm/radeon/radeon_legacy_tv.c
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@ -57,6 +57,10 @@
#define NTSC_TV_PLL_N_14 693 #define NTSC_TV_PLL_N_14 693
#define NTSC_TV_PLL_P_14 7 #define NTSC_TV_PLL_P_14 7
#define PAL_TV_PLL_M_14 19
#define PAL_TV_PLL_N_14 353
#define PAL_TV_PLL_P_14 5
#define VERT_LEAD_IN_LINES 2 #define VERT_LEAD_IN_LINES 2
#define FRAC_BITS 0xe #define FRAC_BITS 0xe
#define FRAC_MASK 0x3fff #define FRAC_MASK 0x3fff
@ -205,9 +209,24 @@ static const struct radeon_tv_mode_constants available_tv_modes[] = {
630627, /* defRestart */ 630627, /* defRestart */
347, /* crtcPLL_N */ 347, /* crtcPLL_N */
14, /* crtcPLL_M */ 14, /* crtcPLL_M */
8, /* crtcPLL_postDiv */ 8, /* crtcPLL_postDiv */
1022, /* pixToTV */ 1022, /* pixToTV */
}, },
{ /* PAL timing for 14 Mhz ref clk */
800, /* horResolution */
600, /* verResolution */
TV_STD_PAL, /* standard */
1131, /* horTotal */
742, /* verTotal */
813, /* horStart */
840, /* horSyncStart */
633, /* verSyncStart */
708369, /* defRestart */
211, /* crtcPLL_N */
9, /* crtcPLL_M */
8, /* crtcPLL_postDiv */
759, /* pixToTV */
},
}; };
#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
@ -242,7 +261,7 @@ static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(stru
if (pll->reference_freq == 2700) if (pll->reference_freq == 2700)
const_ptr = &available_tv_modes[1]; const_ptr = &available_tv_modes[1];
else else
const_ptr = &available_tv_modes[1]; /* FIX ME */ const_ptr = &available_tv_modes[3];
} }
return const_ptr; return const_ptr;
} }
@ -685,9 +704,9 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
n = PAL_TV_PLL_N_27; n = PAL_TV_PLL_N_27;
p = PAL_TV_PLL_P_27; p = PAL_TV_PLL_P_27;
} else { } else {
m = PAL_TV_PLL_M_27; m = PAL_TV_PLL_M_14;
n = PAL_TV_PLL_N_27; n = PAL_TV_PLL_N_14;
p = PAL_TV_PLL_P_27; p = PAL_TV_PLL_P_14;
} }
} }