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arm64: dts: renesas: r8a7795: Create thermal zone to support IPA
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. In R-Car Gen3, IPA is supported for only one channel (on H3/M3/M3N SoCs, it is channel THS3). Reason: Currently, IPA controls base on only CPU temperature. And only one thermal channel is assembled closest CPU cores is selected as target of IPA. If other channels are used, IPA controlling is not properly. The A5 cooling device supports 5 cooling states which can be categorised as follows: 0 & 1) boost (clocking up) 2) default 3 & 4) cooling (clocking down) Currently the thermal framework assumes that the default is the minimum, or in other words there is no provision for handling boost states. So this patch only describes the upper 3 states, default and cooling. A single cooling device is described for all A57 CPUs and a separate cooling device is described for all A53 CPUs. This reflects that physically there is only one cooling device present for each type of CPU. This patch improves on an earlier version by: * Omitting cooling-max-level and cooling-min-level properties which are no longer present in mainline as of v4.17 * Removing an unused trip-point0 node sub-property from the trips property. * Using cooling-device indexes such that maximum refers to maximum cooling rather than the inverse. * Defers adding dynamic-power-coefficient properties to a separate patch as these are properties of the CPU. The long signed-off by chain below reflects many revisions, mainly internal, that this patch has been through. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Hien Dang <hien.dang.eb@rvc.renesas.com> Signed-off-by: An Huynh <an.huynh.uj@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -207,6 +207,7 @@ a53_0: cpu@100 {
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power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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@ -3179,58 +3180,30 @@ sensor_thermal1: sensor-thermal1 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsc 0>;
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sustainable-power = <6313>;
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trips {
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sensor1_passive: sensor1-passive {
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temperature = <95000>;
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hysteresis = <1000>;
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type = "passive";
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};
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sensor1_crit: sensor1-crit {
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temperature = <120000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&sensor1_passive>;
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cooling-device = <&a57_0 4 4>,
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<&a57_1 4 4>,
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<&a57_2 4 4>,
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<&a57_3 4 4>;
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};
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};
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};
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sensor_thermal2: sensor-thermal2 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsc 1>;
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sustainable-power = <6313>;
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trips {
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sensor2_passive: sensor2-passive {
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temperature = <95000>;
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hysteresis = <1000>;
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type = "passive";
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};
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sensor2_crit: sensor2-crit {
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temperature = <120000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&sensor2_passive>;
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cooling-device = <&a57_0 4 4>,
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<&a57_1 4 4>,
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<&a57_2 4 4>,
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<&a57_3 4 4>;
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};
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};
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};
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sensor_thermal3: sensor-thermal3 {
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@ -3239,11 +3212,12 @@ sensor_thermal3: sensor-thermal3 {
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thermal-sensors = <&tsc 2>;
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trips {
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sensor3_passive: sensor3-passive {
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temperature = <95000>;
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target: trip-point1 {
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temperature = <100000>;
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hysteresis = <1000>;
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type = "passive";
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};
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sensor3_crit: sensor3-crit {
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temperature = <120000>;
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hysteresis = <1000>;
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@ -3253,11 +3227,15 @@ sensor3_crit: sensor3-crit {
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cooling-maps {
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map0 {
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trip = <&sensor3_passive>;
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cooling-device = <&a57_0 4 4>,
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<&a57_1 4 4>,
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<&a57_2 4 4>,
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<&a57_3 4 4>;
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trip = <&target>;
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cooling-device = <&a57_0 2 4>;
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contribution = <1024>;
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};
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map1 {
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trip = <&target>;
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cooling-device = <&a53_0 0 2>;
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contribution = <1024>;
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};
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};
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};
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