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drm-misc-next for 4.20:

Browse Source 
UAPI Changes:
 - None
 
 Cross-subsystem Changes:
 - MAINTAINERS: Move udl, mxsfb, and fsl-dcu into drm-misc (Stefan, Sean)
 
 Core Changes:
 - syncobj: Check condition before returning timeout in schedule() (Chris)
 
 Driver Changes:
 - various: First wave o fdrm_fbdev_generic_setup() conversions (Noralf)
 - bochs/virtio: More format byte-order improvements (Gerd)
 - mxsfb: A couple fixes + add runtime pm support (Leonard)
 - virtio: Add vmap support for prime objects (Ezequiel)
 
 Cc: Stefan Agner <stefan@agner.ch>
 Cc: Sean Paul <sean@poorly.run>
 Cc: Noralf Trønnes <noralf@tronnes.org>
 Cc: Gerd Hoffman <kraxel@redhat.com>
 Cc: Leonard Crestez <leonard.crestez@nxp.com>
 Cc: Chris Wilson <chris@chris-wilson.co.uk>
 Cc: Ezequiel Garcia <ezequiel@collabora.com>
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Merge tag 'drm-misc-next-2018-09-27' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for 4.20:

UAPI Changes:
- None

Cross-subsystem Changes:
- MAINTAINERS: Move udl, mxsfb, and fsl-dcu into drm-misc (Stefan, Sean)

Core Changes:
- syncobj: Check condition before returning timeout in schedule() (Chris)

Driver Changes:
- various: First wave of drm_fbdev_generic_setup() conversions (Noralf)
- bochs/virtio: More format byte-order improvements (Gerd)
- mxsfb: A couple fixes + add runtime pm support (Leonard)
- virtio: Add vmap support for prime objects (Ezequiel)

Cc: Stefan Agner <stefan@agner.ch>
Cc: Sean Paul <sean@poorly.run>
Cc: Noralf Trønnes <noralf@tronnes.org>
Cc: Gerd Hoffman <kraxel@redhat.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20180927093950.GA180365@art_vandelay
This commit is contained in:
Dave Airlie 2018-09-28 09:31:03 +10:00
commit 156e60bc71
41 changed files with 367 additions and 282 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
View File

@ -376,6 +376,8 @@ Required properties:
* allwinner,sun8i-a83t-de2-mixer-0
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-r40-de2-mixer-0
* allwinner,sun8i-r40-de2-mixer-1
* allwinner,sun8i-v3s-de2-mixer
* allwinner,sun50i-a64-de2-mixer-0
* allwinner,sun50i-a64-de2-mixer-1

7
MAINTAINERS
View File

@ -4721,8 +4721,11 @@ F: drivers/gpu/drm/tdfx/
DRM DRIVER FOR USB DISPLAYLINK VIDEO ADAPTERS
M: Dave Airlie <airlied@redhat.com>
R: Sean Paul <sean@poorly.run>
L: dri-devel@lists.freedesktop.org
S: Odd Fixes
F: drivers/gpu/drm/udl/
T: git git://anongit.freedesktop.org/drm/drm-misc
DRM DRIVER FOR VMWARE VIRTUAL GPU
M: "VMware Graphics" <linux-graphics-maintainer@vmware.com>
@ -4822,6 +4825,7 @@ F: drivers/gpu/drm/fsl-dcu/
F: Documentation/devicetree/bindings/display/fsl,dcu.txt
F: Documentation/devicetree/bindings/display/fsl,tcon.txt
F: Documentation/devicetree/bindings/display/panel/nec,nl4827hc19-05b.txt
T: git git://anongit.freedesktop.org/drm/drm-misc
DRM DRIVERS FOR FREESCALE IMX
M: Philipp Zabel <p.zabel@pengutronix.de>
@ -9906,9 +9910,12 @@ F: drivers/media/tuners/mxl5007t.*
MXSFB DRM DRIVER
M: Marek Vasut <marex@denx.de>
M: Stefan Agner <stefan@agner.ch>
L: dri-devel@lists.freedesktop.org
S: Supported
F: drivers/gpu/drm/mxsfb/
F: Documentation/devicetree/bindings/display/mxsfb.txt
T: git git://anongit.freedesktop.org/drm/drm-misc
MYRICOM MYRI-10G 10GbE DRIVER (MYRI10GE)
M: Chris Lee <christopher.lee@cspi.com>

11
drivers/gpu/drm/arm/hdlcd_drv.c
View File

@ -103,7 +103,6 @@ static int hdlcd_load(struct drm_device *drm, unsigned long flags)
static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
@ -233,7 +232,6 @@ static struct drm_driver hdlcd_driver = {
.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
DRIVER_MODESET | DRIVER_PRIME |
DRIVER_ATOMIC,
.lastclose = drm_fb_helper_lastclose,
.irq_handler = hdlcd_irq,
.irq_preinstall = hdlcd_irq_preinstall,
.irq_postinstall = hdlcd_irq_postinstall,
@ -308,19 +306,15 @@ static int hdlcd_drm_bind(struct device *dev)
drm_mode_config_reset(drm);
drm_kms_helper_poll_init(drm);
ret = drm_fb_cma_fbdev_init(drm, 32, 0);
if (ret)
goto err_fbdev;
ret = drm_dev_register(drm, 0);
if (ret)
goto err_register;
drm_fbdev_generic_setup(drm, 32);
return 0;
err_register:
drm_fb_cma_fbdev_fini(drm);
err_fbdev:
drm_kms_helper_poll_fini(drm);
err_vblank:
pm_runtime_disable(drm->dev);
@ -346,7 +340,6 @@ static void hdlcd_drm_unbind(struct device *dev)
struct hdlcd_drm_private *hdlcd = drm->dev_private;
drm_dev_unregister(drm);
drm_fb_cma_fbdev_fini(drm);
drm_kms_helper_poll_fini(drm);
component_unbind_all(dev, drm);
of_node_put(hdlcd->crtc.port);

11
drivers/gpu/drm/arm/malidp_drv.c
View File

@ -260,7 +260,6 @@ static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
@ -450,7 +449,6 @@ static int malidp_debugfs_init(struct drm_minor *minor)
static struct drm_driver malidp_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
DRIVER_PRIME,
.lastclose = drm_fb_helper_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = malidp_dumb_create,
@ -762,22 +760,18 @@ static int malidp_bind(struct device *dev)
drm_mode_config_reset(drm);
ret = drm_fb_cma_fbdev_init(drm, 32, 0);
if (ret)
goto fbdev_fail;
drm_kms_helper_poll_init(drm);
ret = drm_dev_register(drm, 0);
if (ret)
goto register_fail;
drm_fbdev_generic_setup(drm, 32);
return 0;
register_fail:
drm_fb_cma_fbdev_fini(drm);
drm_kms_helper_poll_fini(drm);
fbdev_fail:
pm_runtime_get_sync(dev);
vblank_fail:
malidp_se_irq_fini(hwdev);
@ -814,7 +808,6 @@ static void malidp_unbind(struct device *dev)
struct malidp_hw_device *hwdev = malidp->dev;
drm_dev_unregister(drm);
drm_fb_cma_fbdev_fini(drm);
drm_kms_helper_poll_fini(drm);
pm_runtime_get_sync(dev);
drm_crtc_vblank_off(&malidp->crtc);

4
drivers/gpu/drm/bochs/bochs.h
View File

@ -58,6 +58,7 @@ struct bochs_device {
void __iomem *fb_map;
unsigned long fb_base;
unsigned long fb_size;
unsigned long qext_size;
/* mode */
u16 xres;
@ -121,7 +122,8 @@ int bochs_hw_init(struct drm_device *dev);
void bochs_hw_fini(struct drm_device *dev);
void bochs_hw_setmode(struct bochs_device *bochs,
struct drm_display_mode *mode);
struct drm_display_mode *mode,
const struct drm_format_info *format);
void bochs_hw_setbase(struct bochs_device *bochs,
int x, int y, u64 addr);

18
drivers/gpu/drm/bochs/bochs_fbdev.c
View File

@ -63,9 +63,8 @@ static int bochsfb_create(struct drm_fb_helper *helper,
mode_cmd.width = sizes->surface_width;
mode_cmd.height = sizes->surface_height;
mode_cmd.pitches[0] = mode_cmd.width * ((sizes->surface_bpp + 7) / 8);
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sizes->surface_depth);
mode_cmd.pitches[0] = sizes->surface_width * 4;
mode_cmd.pixel_format = DRM_FORMAT_HOST_XRGB8888;
size = mode_cmd.pitches[0] * mode_cmd.height;
/* alloc, pin & map bo */
@ -137,8 +136,19 @@ static const struct drm_fb_helper_funcs bochs_fb_helper_funcs = {
.fb_probe = bochsfb_create,
};
static struct drm_framebuffer *
bochs_gem_fb_create(struct drm_device *dev, struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd)
{
if (mode_cmd->pixel_format != DRM_FORMAT_XRGB8888 &&
mode_cmd->pixel_format != DRM_FORMAT_BGRX8888)
return ERR_PTR(-EINVAL);
return drm_gem_fb_create(dev, file, mode_cmd);
}
const struct drm_mode_config_funcs bochs_mode_funcs = {
.fb_create = drm_gem_fb_create,
.fb_create = bochs_gem_fb_create,
};
int bochs_fbdev_init(struct bochs_device *bochs)

64
drivers/gpu/drm/bochs/bochs_hw.c
View File

@ -47,11 +47,33 @@ static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
}
}
static void bochs_hw_set_big_endian(struct bochs_device *bochs)
{
if (bochs->qext_size < 8)
return;
writel(0xbebebebe, bochs->mmio + 0x604);
}
static void bochs_hw_set_little_endian(struct bochs_device *bochs)
{
if (bochs->qext_size < 8)
return;
writel(0x1e1e1e1e, bochs->mmio + 0x604);
}
#ifdef __BIG_ENDIAN
#define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
#else
#define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
#endif
int bochs_hw_init(struct drm_device *dev)
{
struct bochs_device *bochs = dev->dev_private;
struct pci_dev *pdev = dev->pdev;
unsigned long addr, size, mem, ioaddr, iosize, qext_size;
unsigned long addr, size, mem, ioaddr, iosize;
u16 id;
if (pdev->resource[2].flags & IORESOURCE_MEM) {
@ -117,19 +139,14 @@ int bochs_hw_init(struct drm_device *dev)
ioaddr);
if (bochs->mmio && pdev->revision >= 2) {
qext_size = readl(bochs->mmio + 0x600);
if (qext_size < 4 || qext_size > iosize)
bochs->qext_size = readl(bochs->mmio + 0x600);
if (bochs->qext_size < 4 || bochs->qext_size > iosize) {
bochs->qext_size = 0;
goto noext;
DRM_DEBUG("Found qemu ext regs, size %ld\n", qext_size);
if (qext_size >= 8) {
#ifdef __BIG_ENDIAN
writel(0xbebebebe, bochs->mmio + 0x604);
#else
writel(0x1e1e1e1e, bochs->mmio + 0x604);
#endif
DRM_DEBUG(" qext endian: 0x%x\n",
readl(bochs->mmio + 0x604));
}
DRM_DEBUG("Found qemu ext regs, size %ld\n",
bochs->qext_size);
bochs_hw_set_native_endian(bochs);
}
noext:
@ -150,7 +167,8 @@ void bochs_hw_fini(struct drm_device *dev)
}
void bochs_hw_setmode(struct bochs_device *bochs,
struct drm_display_mode *mode)
struct drm_display_mode *mode,
const struct drm_format_info *format)
{
bochs->xres = mode->hdisplay;
bochs->yres = mode->vdisplay;
@ -158,8 +176,12 @@ void bochs_hw_setmode(struct bochs_device *bochs,
bochs->stride = mode->hdisplay * (bochs->bpp / 8);
bochs->yres_virtual = bochs->fb_size / bochs->stride;
DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
DRM_DEBUG_DRIVER("%dx%d @ %d bpp, format %c%c%c%c, vy %d\n",
bochs->xres, bochs->yres, bochs->bpp,
(format->format >> 0) & 0xff,
(format->format >> 8) & 0xff,
(format->format >> 16) & 0xff,
(format->format >> 24) & 0xff,
bochs->yres_virtual);
bochs_vga_writeb(bochs, 0x3c0, 0x20); /* unblank */
@ -177,6 +199,20 @@ void bochs_hw_setmode(struct bochs_device *bochs,
bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
switch (format->format) {
case DRM_FORMAT_XRGB8888:
bochs_hw_set_little_endian(bochs);
break;
case DRM_FORMAT_BGRX8888:
bochs_hw_set_big_endian(bochs);
break;
default:
/* should not happen */
DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
__func__, format->format);
break;
};
}
void bochs_hw_setbase(struct bochs_device *bochs,

40
drivers/gpu/drm/bochs/bochs_kms.c
View File

@ -77,7 +77,10 @@ static int bochs_crtc_mode_set(struct drm_crtc *crtc,
struct bochs_device *bochs =
container_of(crtc, struct bochs_device, crtc);
bochs_hw_setmode(bochs, mode);
if (WARN_ON(crtc->primary->fb == NULL))
return -EINVAL;
bochs_hw_setmode(bochs, mode, crtc->primary->fb->format);
bochs_crtc_mode_set_base(crtc, x, y, old_fb);
return 0;
}
@ -126,12 +129,44 @@ static const struct drm_crtc_helper_funcs bochs_helper_funcs = {
.commit = bochs_crtc_commit,
};
static const uint32_t bochs_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_BGRX8888,
};
static struct drm_plane *bochs_primary_plane(struct drm_device *dev)
{
struct drm_plane *primary;
int ret;
primary = kzalloc(sizeof(*primary), GFP_KERNEL);
if (primary == NULL) {
DRM_DEBUG_KMS("Failed to allocate primary plane\n");
return NULL;
}
ret = drm_universal_plane_init(dev, primary, 0,
&drm_primary_helper_funcs,
bochs_formats,
ARRAY_SIZE(bochs_formats),
NULL,
DRM_PLANE_TYPE_PRIMARY, NULL);
if (ret) {
kfree(primary);
primary = NULL;
}
return primary;
}
static void bochs_crtc_init(struct drm_device *dev)
{
struct bochs_device *bochs = dev->dev_private;
struct drm_crtc *crtc = &bochs->crtc;
struct drm_plane *primary = bochs_primary_plane(dev);
drm_crtc_init(dev, crtc, &bochs_crtc_funcs);
drm_crtc_init_with_planes(dev, crtc, primary, NULL,
&bochs_crtc_funcs, NULL);
drm_crtc_helper_add(crtc, &bochs_helper_funcs);
}
@ -250,6 +285,7 @@ int bochs_kms_init(struct bochs_device *bochs)
bochs->dev->mode_config.fb_base = bochs->fb_base;
bochs->dev->mode_config.preferred_depth = 24;
bochs->dev->mode_config.prefer_shadow = 0;
bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
bochs->dev->mode_config.funcs = &bochs_mode_funcs;

4
drivers/gpu/drm/drm_atomic_helper.c
View File

@ -3569,9 +3569,7 @@ void __drm_atomic_helper_plane_reset(struct drm_plane *plane,
state->plane = plane;
state->rotation = DRM_MODE_ROTATE_0;
/* Reset the alpha value to fully opaque if it matters */
if (plane->alpha_property)
state->alpha = plane->alpha_property->values[1];
state->alpha = DRM_BLEND_ALPHA_OPAQUE;
state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
plane->state = state;

8
drivers/gpu/drm/drm_fb_helper.c
View File

@ -2843,7 +2843,7 @@ int drm_fb_helper_fbdev_setup(struct drm_device *dev,
if (!max_conn_count)
max_conn_count = dev->mode_config.num_connector;
if (!max_conn_count) {
DRM_DEV_ERROR(dev->dev, "No connectors\n");
DRM_DEV_ERROR(dev->dev, "fbdev: No connectors\n");
return -EINVAL;
}
@ -2851,13 +2851,13 @@ int drm_fb_helper_fbdev_setup(struct drm_device *dev,
ret = drm_fb_helper_init(dev, fb_helper, max_conn_count);
if (ret < 0) {
DRM_DEV_ERROR(dev->dev, "Failed to initialize fbdev helper\n");
DRM_DEV_ERROR(dev->dev, "fbdev: Failed to initialize (ret=%d)\n", ret);
return ret;
}
ret = drm_fb_helper_single_add_all_connectors(fb_helper);
if (ret < 0) {
DRM_DEV_ERROR(dev->dev, "Failed to add connectors\n");
DRM_DEV_ERROR(dev->dev, "fbdev: Failed to add connectors (ret=%d)\n", ret);
goto err_drm_fb_helper_fini;
}
@ -2866,7 +2866,7 @@ int drm_fb_helper_fbdev_setup(struct drm_device *dev,
ret = drm_fb_helper_initial_config(fb_helper, preferred_bpp);
if (ret < 0) {
DRM_DEV_ERROR(dev->dev, "Failed to set fbdev configuration\n");
DRM_DEV_ERROR(dev->dev, "fbdev: Failed to set configuration (ret=%d)\n", ret);
goto err_drm_fb_helper_fini;
}

35
drivers/gpu/drm/drm_fourcc.c
View File

@ -95,6 +95,41 @@ uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)
}
EXPORT_SYMBOL(drm_mode_legacy_fb_format);
/**
* drm_driver_legacy_fb_format - compute drm fourcc code from legacy description
* @bpp: bits per pixels
* @depth: bit depth per pixel
* @native: use host native byte order
*
* Computes a drm fourcc pixel format code for the given @bpp/@depth values.
* Unlike drm_mode_legacy_fb_format() this looks at the drivers mode_config,
* and depending on the quirk_addfb_prefer_host_byte_order flag it returns
* little endian byte order or host byte order framebuffer formats.
*/
uint32_t drm_driver_legacy_fb_format(struct drm_device *dev,
uint32_t bpp, uint32_t depth)
{
uint32_t fmt = drm_mode_legacy_fb_format(bpp, depth);
if (dev->mode_config.quirk_addfb_prefer_host_byte_order) {
if (fmt == DRM_FORMAT_XRGB8888)
fmt = DRM_FORMAT_HOST_XRGB8888;
if (fmt == DRM_FORMAT_ARGB8888)
fmt = DRM_FORMAT_HOST_ARGB8888;
if (fmt == DRM_FORMAT_RGB565)
fmt = DRM_FORMAT_HOST_RGB565;
if (fmt == DRM_FORMAT_XRGB1555)
fmt = DRM_FORMAT_HOST_XRGB1555;
}
if (dev->mode_config.quirk_addfb_prefer_xbgr_30bpp &&
fmt == DRM_FORMAT_XRGB2101010)
fmt = DRM_FORMAT_XBGR2101010;
return fmt;
}
EXPORT_SYMBOL(drm_driver_legacy_fb_format);
/**
* drm_get_format_name - fill a string with a drm fourcc format's name
* @format: format to compute name of

17
drivers/gpu/drm/drm_framebuffer.c
View File

@ -116,7 +116,7 @@ int drm_mode_addfb(struct drm_device *dev, struct drm_mode_fb_cmd *or,
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -EOPNOTSUPP;
r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
r.pixel_format = drm_driver_legacy_fb_format(dev, or->bpp, or->depth);
if (r.pixel_format == DRM_FORMAT_INVALID) {
DRM_DEBUG("bad {bpp:%d, depth:%d}\n", or->bpp, or->depth);
return -EINVAL;
@ -129,21 +129,6 @@ int drm_mode_addfb(struct drm_device *dev, struct drm_mode_fb_cmd *or,
r.pitches[0] = or->pitch;
r.handles[0] = or->handle;
if (dev->mode_config.quirk_addfb_prefer_xbgr_30bpp &&
r.pixel_format == DRM_FORMAT_XRGB2101010)
r.pixel_format = DRM_FORMAT_XBGR2101010;
if (dev->mode_config.quirk_addfb_prefer_host_byte_order) {
if (r.pixel_format == DRM_FORMAT_XRGB8888)
r.pixel_format = DRM_FORMAT_HOST_XRGB8888;
if (r.pixel_format == DRM_FORMAT_ARGB8888)
r.pixel_format = DRM_FORMAT_HOST_ARGB8888;
if (r.pixel_format == DRM_FORMAT_RGB565)
r.pixel_format = DRM_FORMAT_HOST_RGB565;
if (r.pixel_format == DRM_FORMAT_XRGB1555)
r.pixel_format = DRM_FORMAT_HOST_XRGB1555;
}
ret = drm_mode_addfb2(dev, &r, file_priv);
if (ret)
return ret;

4
drivers/gpu/drm/drm_gem_framebuffer_helper.c
View File

@ -316,8 +316,8 @@ drm_gem_fbdev_fb_create(struct drm_device *dev,
if (pitch_align)
mode_cmd.pitches[0] = roundup(mode_cmd.pitches[0],
pitch_align);
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sizes->surface_depth);
mode_cmd.pixel_format = drm_driver_legacy_fb_format(dev, sizes->surface_bpp,
sizes->surface_depth);
if (obj->size < mode_cmd.pitches[0] * mode_cmd.height)
return ERR_PTR(-EINVAL);

6
drivers/gpu/drm/drm_ioctl.c
View File

@ -306,6 +306,12 @@ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
struct drm_set_client_cap *req = data;
/* No render-only settable capabilities for now */
/* Below caps that only works with KMS drivers */
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -EOPNOTSUPP;
switch (req->capability) {
case DRM_CLIENT_CAP_STEREO_3D:
if (req->value > 1)

52
drivers/gpu/drm/drm_syncobj.c
View File

@ -66,20 +66,9 @@ static const char *drm_syncobj_stub_fence_get_name(struct dma_fence *fence)
return "syncobjstub";
}
static bool drm_syncobj_stub_fence_enable_signaling(struct dma_fence *fence)
{
return !dma_fence_is_signaled(fence);
}
static void drm_syncobj_stub_fence_release(struct dma_fence *f)
{
kfree(f);
}
static const struct dma_fence_ops drm_syncobj_stub_fence_ops = {
.get_driver_name = drm_syncobj_stub_fence_get_name,
.get_timeline_name = drm_syncobj_stub_fence_get_name,
.enable_signaling = drm_syncobj_stub_fence_enable_signaling,
.release = drm_syncobj_stub_fence_release,
};
@ -683,7 +672,6 @@ static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs,
{
struct syncobj_wait_entry *entries;
struct dma_fence *fence;
signed long ret;
uint32_t signaled_count, i;
entries = kcalloc(count, sizeof(*entries), GFP_KERNEL);
@ -703,7 +691,7 @@ static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs,
if (flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT) {
continue;
} else {
ret = -EINVAL;
timeout = -EINVAL;
goto cleanup_entries;
}
}
@ -715,12 +703,6 @@ static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs,
}
}
/* Initialize ret to the max of timeout and 1. That way, the
* default return value indicates a successful wait and not a
* timeout.
*/
ret = max_t(signed long, timeout, 1);
if (signaled_count == count ||
(signaled_count > 0 &&
!(flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL)))
@ -771,18 +753,17 @@ static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs,
goto done_waiting;
if (timeout == 0) {
/* If we are doing a 0 timeout wait and we got
* here, then we just timed out.
*/
ret = 0;
timeout = -ETIME;
goto done_waiting;
}
ret = schedule_timeout(ret);
if (signal_pending(current)) {
timeout = -ERESTARTSYS;
goto done_waiting;
}
if (ret > 0 && signal_pending(current))
ret = -ERESTARTSYS;
} while (ret > 0);
timeout = schedule_timeout(timeout);
} while (1);
done_waiting:
__set_current_state(TASK_RUNNING);
@ -799,7 +780,7 @@ static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs,
}
kfree(entries);
return ret;
return timeout;
}
/**
@ -840,19 +821,16 @@ static int drm_syncobj_array_wait(struct drm_device *dev,
struct drm_syncobj **syncobjs)
{
signed long timeout = drm_timeout_abs_to_jiffies(wait->timeout_nsec);
signed long ret = 0;
uint32_t first = ~0;
ret = drm_syncobj_array_wait_timeout(syncobjs,
wait->count_handles,
wait->flags,
timeout, &first);
if (ret < 0)
return ret;
timeout = drm_syncobj_array_wait_timeout(syncobjs,
wait->count_handles,
wait->flags,
timeout, &first);
if (timeout < 0)
return timeout;
wait->first_signaled = first;
if (ret == 0)
return -ETIME;
return 0;
}

8
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
View File

@ -353,12 +353,12 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
ret = drm_dev_register(drm, 0);
if (ret < 0)
goto unref;
goto put;
return 0;
unref:
drm_dev_unref(drm);
put:
drm_dev_put(drm);
unregister_pix_clk:
clk_unregister(fsl_dev->pix_clk);
disable_clk:
@ -371,7 +371,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
drm_dev_unregister(fsl_dev->drm);
drm_dev_unref(fsl_dev->drm);
drm_dev_put(fsl_dev->drm);
clk_disable_unprepare(fsl_dev->clk);
clk_unregister(fsl_dev->pix_clk);

19
drivers/gpu/drm/imx/imx-drm-core.c
View File

@ -86,7 +86,6 @@ static int imx_drm_atomic_check(struct drm_device *dev,
static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = imx_drm_atomic_check,
.atomic_commit = drm_atomic_helper_commit,
};
@ -165,7 +164,6 @@ static const struct drm_ioctl_desc imx_drm_ioctls[] = {
static struct drm_driver imx_drm_driver = {
.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
DRIVER_ATOMIC,
.lastclose = drm_fb_helper_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = drm_gem_cma_dumb_create,
@ -263,30 +261,23 @@ static int imx_drm_bind(struct device *dev)
* The fb helper takes copies of key hardware information, so the
* crtcs/connectors/encoders must not change after this point.
*/
#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION)
if (legacyfb_depth != 16 && legacyfb_depth != 32) {
dev_warn(dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
legacyfb_depth = 16;
}
ret = drm_fb_cma_fbdev_init(drm, legacyfb_depth, MAX_CRTC);
if (ret)
goto err_unbind;
#endif
drm_kms_helper_poll_init(drm);
ret = drm_dev_register(drm, 0);
if (ret)
goto err_fbhelper;
goto err_poll_fini;
drm_fbdev_generic_setup(drm, legacyfb_depth);
return 0;
err_fbhelper:
err_poll_fini:
drm_kms_helper_poll_fini(drm);
#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION)
drm_fb_cma_fbdev_fini(drm);
err_unbind:
#endif
component_unbind_all(drm->dev, drm);
err_kms:
drm_mode_config_cleanup(drm);
@ -303,8 +294,6 @@ static void imx_drm_unbind(struct device *dev)
drm_kms_helper_poll_fini(drm);
drm_fb_cma_fbdev_fini(drm);
drm_mode_config_cleanup(drm);
component_unbind_all(drm->dev, drm);

53
drivers/gpu/drm/mxsfb/mxsfb_crtc.c
View File

@ -129,7 +129,6 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
if (mxsfb->clk_disp_axi)
clk_prepare_enable(mxsfb->clk_disp_axi);
clk_prepare_enable(mxsfb->clk);
mxsfb_enable_axi_clk(mxsfb);
/* If it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
@ -159,8 +158,6 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
reg &= ~VDCTRL4_SYNC_SIGNALS_ON;
writel(reg, mxsfb->base + LCDC_VDCTRL4);
mxsfb_disable_axi_clk(mxsfb);
clk_disable_unprepare(mxsfb->clk);
if (mxsfb->clk_disp_axi)
clk_disable_unprepare(mxsfb->clk_disp_axi);
@ -196,6 +193,21 @@ static int mxsfb_reset_block(void __iomem *reset_addr)
return clear_poll_bit(reset_addr, MODULE_CLKGATE);
}
static dma_addr_t mxsfb_get_fb_paddr(struct mxsfb_drm_private *mxsfb)
{
struct drm_framebuffer *fb = mxsfb->pipe.plane.state->fb;
struct drm_gem_cma_object *gem;
if (!fb)
return 0;
gem = drm_fb_cma_get_gem_obj(fb, 0);
if (!gem)
return 0;
return gem->paddr;
}
static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
{
struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
@ -208,7 +220,6 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
* running. This may lead to shifted pictures (FIFO issue?), so
* first stop the controller and drain its FIFOs.
*/
mxsfb_enable_axi_clk(mxsfb);
/* Mandatory eLCDIF reset as per the Reference Manual */
err = mxsfb_reset_block(mxsfb->base);
@ -269,19 +280,29 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay),
mxsfb->base + LCDC_VDCTRL4);
mxsfb_disable_axi_clk(mxsfb);
}
void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
{
dma_addr_t paddr;
mxsfb_enable_axi_clk(mxsfb);
mxsfb_crtc_mode_set_nofb(mxsfb);
/* Write cur_buf as well to avoid an initial corrupt frame */
paddr = mxsfb_get_fb_paddr(mxsfb);
if (paddr) {
writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf);
writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
}
mxsfb_enable_controller(mxsfb);
}
void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
{
mxsfb_disable_controller(mxsfb);
mxsfb_disable_axi_clk(mxsfb);
}
void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
@ -289,12 +310,8 @@ void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
{
struct drm_simple_display_pipe *pipe = &mxsfb->pipe;
struct drm_crtc *crtc = &pipe->crtc;
struct drm_framebuffer *fb = pipe->plane.state->fb;
struct drm_pending_vblank_event *event;
struct drm_gem_cma_object *gem;
if (!crtc)
return;
dma_addr_t paddr;
spin_lock_irq(&crtc->dev->event_lock);
event = crtc->state->event;
@ -309,12 +326,10 @@ void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
}
spin_unlock_irq(&crtc->dev->event_lock);
if (!fb)
return;
gem = drm_fb_cma_get_gem_obj(fb, 0);
mxsfb_enable_axi_clk(mxsfb);
writel(gem->paddr, mxsfb->base + mxsfb->devdata->next_buf);
mxsfb_disable_axi_clk(mxsfb);
paddr = mxsfb_get_fb_paddr(mxsfb);
if (paddr) {
mxsfb_enable_axi_clk(mxsfb);
writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
mxsfb_disable_axi_clk(mxsfb);
}
}

40
drivers/gpu/drm/mxsfb/mxsfb_drv.c
View File

@ -98,12 +98,18 @@ static const struct drm_mode_config_funcs mxsfb_mode_config_funcs = {
.atomic_commit = drm_atomic_helper_commit,
};
static const struct drm_mode_config_helper_funcs mxsfb_mode_config_helpers = {
.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
};
static void mxsfb_pipe_enable(struct drm_simple_display_pipe *pipe,
struct drm_crtc_state *crtc_state,
struct drm_plane_state *plane_state)
{
struct mxsfb_drm_private *mxsfb = drm_pipe_to_mxsfb_drm_private(pipe);
struct drm_device *drm = pipe->plane.dev;
pm_runtime_get_sync(drm->dev);
drm_panel_prepare(mxsfb->panel);
mxsfb_crtc_enable(mxsfb);
drm_panel_enable(mxsfb->panel);
@ -112,10 +118,22 @@ static void mxsfb_pipe_enable(struct drm_simple_display_pipe *pipe,
static void mxsfb_pipe_disable(struct drm_simple_display_pipe *pipe)
{
struct mxsfb_drm_private *mxsfb = drm_pipe_to_mxsfb_drm_private(pipe);
struct drm_device *drm = pipe->plane.dev;
struct drm_crtc *crtc = &pipe->crtc;
struct drm_pending_vblank_event *event;
drm_panel_disable(mxsfb->panel);
mxsfb_crtc_disable(mxsfb);
drm_panel_unprepare(mxsfb->panel);
pm_runtime_put_sync(drm->dev);
spin_lock_irq(&drm->event_lock);
event = crtc->state->event;
if (event) {
crtc->state->event = NULL;
drm_crtc_send_vblank_event(crtc, event);
}
spin_unlock_irq(&drm->event_lock);
}
static void mxsfb_pipe_update(struct drm_simple_display_pipe *pipe,
@ -230,6 +248,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
drm->mode_config.max_width = MXSFB_MAX_XRES;
drm->mode_config.max_height = MXSFB_MAX_YRES;
drm->mode_config.funcs = &mxsfb_mode_config_funcs;
drm->mode_config.helper_private = &mxsfb_mode_config_helpers;
drm_mode_config_reset(drm);
@ -414,6 +433,26 @@ static int mxsfb_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int mxsfb_suspend(struct device *dev)
{
struct drm_device *drm = dev_get_drvdata(dev);
return drm_mode_config_helper_suspend(drm);
}
static int mxsfb_resume(struct device *dev)
{
struct drm_device *drm = dev_get_drvdata(dev);
return drm_mode_config_helper_resume(drm);
}
#endif
static const struct dev_pm_ops mxsfb_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(mxsfb_suspend, mxsfb_resume)
};
static struct platform_driver mxsfb_platform_driver = {
.probe = mxsfb_probe,
.remove = mxsfb_remove,
@ -421,6 +460,7 @@ static struct platform_driver mxsfb_platform_driver = {
.driver = {
.name = "mxsfb",
.of_match_table = mxsfb_dt_ids,
.pm = &mxsfb_pm_ops,
},
};

6
drivers/gpu/drm/pl111/pl111_drv.c
View File

@ -194,8 +194,6 @@ static int pl111_modeset_init(struct drm_device *dev)
drm_mode_config_reset(dev);
drm_fb_cma_fbdev_init(dev, priv->variant->fb_bpp, 0);
drm_kms_helper_poll_init(dev);
goto finish;
@ -232,7 +230,6 @@ DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
static struct drm_driver pl111_drm_driver = {
.driver_features =
DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
.lastclose = drm_fb_helper_lastclose,
.ioctls = NULL,
.fops = &drm_fops,
.name = "pl111",
@ -332,6 +329,8 @@ static int pl111_amba_probe(struct amba_device *amba_dev,
if (ret < 0)
goto dev_put;
drm_fbdev_generic_setup(drm, priv->variant->fb_bpp);
return 0;
dev_put:
@ -348,7 +347,6 @@ static int pl111_amba_remove(struct amba_device *amba_dev)
struct pl111_drm_dev_private *priv = drm->dev_private;
drm_dev_unregister(drm);
drm_fb_cma_fbdev_fini(drm);
if (priv->panel)
drm_panel_bridge_remove(priv->bridge);
drm_mode_config_cleanup(drm);

8
drivers/gpu/drm/sti/sti_drv.c
View File

@ -121,7 +121,6 @@ static int sti_drm_dbg_init(struct drm_minor *minor)
static const struct drm_mode_config_funcs sti_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
@ -206,7 +205,6 @@ static void sti_cleanup(struct drm_device *ddev)
{
struct sti_private *private = ddev->dev_private;
drm_fb_cma_fbdev_fini(ddev);
drm_kms_helper_poll_fini(ddev);
component_unbind_all(ddev->dev, ddev);
kfree(private);
@ -236,11 +234,7 @@ static int sti_bind(struct device *dev)
drm_mode_config_reset(ddev);
if (ddev->mode_config.num_connector) {
ret = drm_fb_cma_fbdev_init(ddev, 32, 0);
if (ret)
DRM_DEBUG_DRIVER("Warning: fails to create fbdev\n");
}
drm_fbdev_generic_setup(ddev, 32);
return 0;

1
drivers/gpu/drm/sun4i/sun4i_drv.c
View File

@ -402,6 +402,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun8i-a33-display-engine" },
{ .compatible = "allwinner,sun8i-a83t-display-engine" },
{ .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-r40-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ .compatible = "allwinner,sun9i-a80-display-engine" },
{ .compatible = "allwinner,sun50i-a64-display-engine" },

24
drivers/gpu/drm/sun4i/sun8i_mixer.c
View File

@ -545,6 +545,22 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
.vi_num = 1,
};
static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
.ccsc = 0,
.mod_rate = 297000000,
.scaler_mask = 0xf,
.ui_num = 3,
.vi_num = 1,
};
static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
.ccsc = 1,
.mod_rate = 297000000,
.scaler_mask = 0x3,
.ui_num = 1,
.vi_num = 1,
};
static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.vi_num = 2,
.ui_num = 1,
@ -582,6 +598,14 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun8i-h3-de2-mixer-0",
.data = &sun8i_h3_mixer0_cfg,
},
{
.compatible = "allwinner,sun8i-r40-de2-mixer-0",
.data = &sun8i_r40_mixer0_cfg,
},
{
.compatible = "allwinner,sun8i-r40-de2-mixer-1",
.data = &sun8i_r40_mixer1_cfg,
},
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,

1
drivers/gpu/drm/sun4i/sun8i_tcon_top.c
View File

@ -252,6 +252,7 @@ static int sun8i_tcon_top_remove(struct platform_device *pdev)
/* sun4i_drv uses this list to check if a device node is a TCON TOP */
const struct of_device_id sun8i_tcon_top_of_table[] = {
{ .compatible = "allwinner,sun8i-r40-tcon-top" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);

10
drivers/gpu/drm/tegra/drm.c
View File

@ -1189,16 +1189,16 @@ static int host1x_drm_probe(struct host1x_device *dev)
err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false);
if (err < 0)
goto unref;
goto put;
err = drm_dev_register(drm, 0);
if (err < 0)
goto unref;
goto put;
return 0;
unref:
drm_dev_unref(drm);
put:
drm_dev_put(drm);
return err;
}
@ -1207,7 +1207,7 @@ static int host1x_drm_remove(struct host1x_device *dev)
struct drm_device *drm = dev_get_drvdata(&dev->dev);
drm_dev_unregister(drm);
drm_dev_unref(drm);
drm_dev_put(drm);
return 0;
}

14
drivers/gpu/drm/tve200/tve200_drv.c
View File

@ -126,12 +126,6 @@ static int tve200_modeset_init(struct drm_device *dev)
}
drm_mode_config_reset(dev);
/*
* Passing in 16 here will make the RGB656 mode the default
* Passing in 32 will use XRGB8888 mode
*/
drm_fb_cma_fbdev_init(dev, 16, 0);
drm_kms_helper_poll_init(dev);
goto finish;
@ -149,7 +143,6 @@ DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
static struct drm_driver tve200_drm_driver = {
.driver_features =
DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
.lastclose = drm_fb_helper_lastclose,
.ioctls = NULL,
.fops = &drm_fops,
.name = "tve200",
@ -245,6 +238,12 @@ static int tve200_probe(struct platform_device *pdev)
if (ret < 0)
goto clk_disable;
/*
* Passing in 16 here will make the RGB565 mode the default
* Passing in 32 will use XRGB8888 mode
*/
drm_fbdev_generic_setup(drm, 16);
return 0;
clk_disable:
@ -260,7 +259,6 @@ static int tve200_remove(struct platform_device *pdev)
struct tve200_drm_dev_private *priv = drm->dev_private;
drm_dev_unregister(drm);
drm_fb_cma_fbdev_fini(drm);
if (priv->panel)
drm_panel_bridge_remove(priv->bridge);
drm_mode_config_cleanup(drm);

2
drivers/gpu/drm/udl/udl_drv.c
View File

@ -94,7 +94,7 @@ static int udl_usb_probe(struct usb_interface *interface,
return 0;
err_free:
drm_dev_unref(dev);
drm_dev_put(dev);
return r;
}

5
drivers/gpu/drm/vc4/vc4_drv.c
View File

@ -178,7 +178,6 @@ static struct drm_driver vc4_drm_driver = {
DRIVER_RENDER |
DRIVER_PRIME |
DRIVER_SYNCOBJ),
.lastclose = drm_fb_helper_lastclose,
.open = vc4_open,
.postclose = vc4_close,
.irq_handler = vc4_irq,
@ -288,6 +287,8 @@ static int vc4_drm_bind(struct device *dev)
vc4_kms_load(drm);
drm_fbdev_generic_setup(drm, 32);
return 0;
unbind_all:
@ -307,8 +308,6 @@ static void vc4_drm_unbind(struct device *dev)
drm_dev_unregister(drm);
drm_fb_cma_fbdev_fini(drm);
drm_mode_config_cleanup(drm);
drm_atomic_private_obj_fini(&vc4->ctm_manager);

6
drivers/gpu/drm/vc4/vc4_kms.c
View File

@ -19,8 +19,6 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include "vc4_drv.h"
#include "vc4_regs.h"
@ -394,7 +392,6 @@ vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
}
static const struct drm_mode_config_funcs vc4_mode_funcs = {
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = vc4_atomic_check,
.atomic_commit = vc4_atomic_commit,
.fb_create = vc4_fb_create,
@ -434,9 +431,6 @@ int vc4_kms_load(struct drm_device *dev)
drm_mode_config_reset(dev);
if (dev->mode_config.num_connector)
drm_fb_cma_fbdev_init(dev, 32, 0);
drm_kms_helper_poll_init(dev);
return 0;

5
drivers/gpu/drm/virtio/virtgpu_display.c
View File

@ -307,6 +307,10 @@ virtio_gpu_user_framebuffer_create(struct drm_device *dev,
struct virtio_gpu_framebuffer *virtio_gpu_fb;
int ret;
if (mode_cmd->pixel_format != DRM_FORMAT_HOST_XRGB8888 &&
mode_cmd->pixel_format != DRM_FORMAT_HOST_ARGB8888)
return ERR_PTR(-ENOENT);
/* lookup object associated with res handle */
obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
if (!obj)
@ -355,6 +359,7 @@ int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev)
int i;
drm_mode_config_init(vgdev->ddev);
vgdev->ddev->mode_config.quirk_addfb_prefer_host_byte_order = true;
vgdev->ddev->mode_config.funcs = &virtio_gpu_mode_funcs;
vgdev->ddev->mode_config.helper_private = &virtio_mode_config_helpers;

9
drivers/gpu/drm/virtio/virtgpu_drv.h
View File

@ -270,7 +270,8 @@ void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
uint32_t resource_id);
void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
uint32_t resource_id, uint64_t offset,
struct virtio_gpu_object *bo,
uint64_t offset,
__le32 width, __le32 height,
__le32 x, __le32 y,
struct virtio_gpu_fence **fence);
@ -316,7 +317,8 @@ void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
struct virtio_gpu_box *box,
struct virtio_gpu_fence **fence);
void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
uint32_t resource_id, uint32_t ctx_id,
struct virtio_gpu_object *bo,
uint32_t ctx_id,
uint64_t offset, uint32_t level,
struct virtio_gpu_box *box,
struct virtio_gpu_fence **fence);
@ -361,7 +363,8 @@ void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
unsigned long size, bool kernel, bool pinned,
struct virtio_gpu_object **bo_ptr);
int virtio_gpu_object_kmap(struct virtio_gpu_object *bo, void **ptr);
void virtio_gpu_object_kunmap(struct virtio_gpu_object *bo);
int virtio_gpu_object_kmap(struct virtio_gpu_object *bo);
int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
struct virtio_gpu_object *bo);
void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo);

14
drivers/gpu/drm/virtio/virtgpu_fb.c
View File

@ -95,7 +95,7 @@ static int virtio_gpu_dirty_update(struct virtio_gpu_framebuffer *fb,
offset = (y * fb->base.pitches[0]) + x * bpp;
virtio_gpu_cmd_transfer_to_host_2d(vgdev, obj->hw_res_handle,
virtio_gpu_cmd_transfer_to_host_2d(vgdev, obj,
offset,
cpu_to_le32(w),
cpu_to_le32(h),
@ -203,12 +203,6 @@ static struct fb_ops virtio_gpufb_ops = {
.fb_imageblit = virtio_gpu_3d_imageblit,
};
static int virtio_gpu_vmap_fb(struct virtio_gpu_device *vgdev,
struct virtio_gpu_object *obj)
{
return virtio_gpu_object_kmap(obj, NULL);
}
static int virtio_gpufb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
@ -226,7 +220,7 @@ static int virtio_gpufb_create(struct drm_fb_helper *helper,
mode_cmd.width = sizes->surface_width;
mode_cmd.height = sizes->surface_height;
mode_cmd.pitches[0] = mode_cmd.width * 4;
mode_cmd.pixel_format = drm_mode_legacy_fb_format(32, 24);
mode_cmd.pixel_format = DRM_FORMAT_HOST_XRGB8888;
format = virtio_gpu_translate_format(mode_cmd.pixel_format);
if (format == 0)
@ -241,9 +235,9 @@ static int virtio_gpufb_create(struct drm_fb_helper *helper,
virtio_gpu_cmd_create_resource(vgdev, resid, format,
mode_cmd.width, mode_cmd.height);
ret = virtio_gpu_vmap_fb(vgdev, obj);
ret = virtio_gpu_object_kmap(obj);
if (ret) {
DRM_ERROR("failed to vmap fb %d\n", ret);
DRM_ERROR("failed to kmap fb %d\n", ret);
goto err_obj_vmap;
}

7
drivers/gpu/drm/virtio/virtgpu_gem.c
View File

@ -90,7 +90,10 @@ int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
uint32_t resid;
uint32_t format;
pitch = args->width * ((args->bpp + 1) / 8);
if (args->bpp != 32)
return -EINVAL;
pitch = args->width * 4;
args->size = pitch * args->height;
args->size = ALIGN(args->size, PAGE_SIZE);
@ -99,7 +102,7 @@ int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
if (ret)
goto fail;
format = virtio_gpu_translate_format(DRM_FORMAT_XRGB8888);
format = virtio_gpu_translate_format(DRM_FORMAT_HOST_XRGB8888);
virtio_gpu_resource_id_get(vgdev, &resid);
virtio_gpu_cmd_create_resource(vgdev, resid, format,
args->width, args->height);

4
drivers/gpu/drm/virtio/virtgpu_ioctl.c
View File

@ -429,11 +429,11 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
convert_to_hw_box(&box, &args->box);
if (!vgdev->has_virgl_3d) {
virtio_gpu_cmd_transfer_to_host_2d
(vgdev, qobj->hw_res_handle, offset,
(vgdev, qobj, offset,
box.w, box.h, box.x, box.y, NULL);
} else {
virtio_gpu_cmd_transfer_to_host_3d
(vgdev, qobj->hw_res_handle,
(vgdev, qobj,
vfpriv ? vfpriv->ctx_id : 0, offset,
args->level, &box, &fence);
reservation_object_add_excl_fence(qobj->tbo.resv,

19
drivers/gpu/drm/virtio/virtgpu_object.c
View File

@ -37,6 +37,8 @@ static void virtio_gpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
virtio_gpu_cmd_unref_resource(vgdev, bo->hw_res_handle);
if (bo->pages)
virtio_gpu_object_free_sg_table(bo);
if (bo->vmap)
virtio_gpu_object_kunmap(bo);
drm_gem_object_release(&bo->gem_base);
kfree(bo);
}
@ -99,22 +101,23 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
return 0;
}
int virtio_gpu_object_kmap(struct virtio_gpu_object *bo, void **ptr)
void virtio_gpu_object_kunmap(struct virtio_gpu_object *bo)
{
bo->vmap = NULL;
ttm_bo_kunmap(&bo->kmap);
}
int virtio_gpu_object_kmap(struct virtio_gpu_object *bo)
{
bool is_iomem;
int r;
if (bo->vmap) {
if (ptr)
*ptr = bo->vmap;
return 0;
}
WARN_ON(bo->vmap);
r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
if (r)
return r;
bo->vmap = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
if (ptr)
*ptr = bo->vmap;
return 0;
}

58
drivers/gpu/drm/virtio/virtgpu_plane.c
View File

@ -28,22 +28,11 @@
#include <drm/drm_atomic_helper.h>
static const uint32_t virtio_gpu_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_BGRX8888,
DRM_FORMAT_BGRA8888,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_HOST_XRGB8888,
};
static const uint32_t virtio_gpu_cursor_formats[] = {
#ifdef __BIG_ENDIAN
DRM_FORMAT_BGRA8888,
#else
DRM_FORMAT_ARGB8888,
#endif
DRM_FORMAT_HOST_ARGB8888,
};
uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
@ -51,32 +40,6 @@ uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
uint32_t format;
switch (drm_fourcc) {
#ifdef __BIG_ENDIAN
case DRM_FORMAT_XRGB8888:
format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
break;
case DRM_FORMAT_ARGB8888:
format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
break;
case DRM_FORMAT_BGRX8888:
format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
break;
case DRM_FORMAT_BGRA8888:
format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
break;
case DRM_FORMAT_RGBX8888:
format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
break;
case DRM_FORMAT_RGBA8888:
format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
break;
case DRM_FORMAT_XBGR8888:
format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
break;
case DRM_FORMAT_ABGR8888:
format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
break;
#else
case DRM_FORMAT_XRGB8888:
format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
break;
@ -89,19 +52,6 @@ uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
case DRM_FORMAT_BGRA8888:
format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
break;
case DRM_FORMAT_RGBX8888:
format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
break;
case DRM_FORMAT_RGBA8888:
format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
break;
case DRM_FORMAT_XBGR8888:
format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
break;
case DRM_FORMAT_ABGR8888:
format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
break;
#endif
default:
/*
* This should not happen, we handle everything listed
@ -158,7 +108,7 @@ static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
handle = bo->hw_res_handle;
if (bo->dumb) {
virtio_gpu_cmd_transfer_to_host_2d
(vgdev, handle, 0,
(vgdev, bo, 0,
cpu_to_le32(plane->state->src_w >> 16),
cpu_to_le32(plane->state->src_h >> 16),
cpu_to_le32(plane->state->src_x >> 16),
@ -217,7 +167,7 @@ static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
/* new cursor -- update & wait */
virtio_gpu_cmd_transfer_to_host_2d
(vgdev, handle, 0,
(vgdev, bo, 0,
cpu_to_le32(plane->state->crtc_w),
cpu_to_le32(plane->state->crtc_h),
0, 0, &fence);

11
drivers/gpu/drm/virtio/virtgpu_prime.c
View File

@ -55,13 +55,18 @@ struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
void *virtgpu_gem_prime_vmap(struct drm_gem_object *obj)
{
WARN_ONCE(1, "not implemented");
return ERR_PTR(-ENODEV);
struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(obj);
int ret;
ret = virtio_gpu_object_kmap(bo);
if (ret)
return NULL;
return bo->vmap;
}
void virtgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
{
WARN_ONCE(1, "not implemented");
virtio_gpu_object_kunmap(gem_to_virtio_gpu_obj(obj));
}
int virtgpu_gem_prime_mmap(struct drm_gem_object *obj,

20
drivers/gpu/drm/virtio/virtgpu_vq.c
View File

@ -483,28 +483,26 @@ void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
}
void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
uint32_t resource_id, uint64_t offset,
struct virtio_gpu_object *bo,
uint64_t offset,
__le32 width, __le32 height,
__le32 x, __le32 y,
struct virtio_gpu_fence **fence)
{
struct virtio_gpu_transfer_to_host_2d *cmd_p;
struct virtio_gpu_vbuffer *vbuf;
struct virtio_gpu_fbdev *vgfbdev = vgdev->vgfbdev;
struct virtio_gpu_framebuffer *fb = &vgfbdev->vgfb;
struct virtio_gpu_object *obj = gem_to_virtio_gpu_obj(fb->base.obj[0]);
bool use_dma_api = !virtio_has_iommu_quirk(vgdev->vdev);
if (use_dma_api)
dma_sync_sg_for_device(vgdev->vdev->dev.parent,
obj->pages->sgl, obj->pages->nents,
bo->pages->sgl, bo->pages->nents,
DMA_TO_DEVICE);
cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
memset(cmd_p, 0, sizeof(*cmd_p));
cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
cmd_p->resource_id = cpu_to_le32(resource_id);
cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
cmd_p->offset = cpu_to_le64(offset);
cmd_p->r.width = width;
cmd_p->r.height = height;
@ -791,21 +789,19 @@ virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
}
void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
uint32_t resource_id, uint32_t ctx_id,
struct virtio_gpu_object *bo,
uint32_t ctx_id,
uint64_t offset, uint32_t level,
struct virtio_gpu_box *box,
struct virtio_gpu_fence **fence)
{
struct virtio_gpu_transfer_host_3d *cmd_p;
struct virtio_gpu_vbuffer *vbuf;
struct virtio_gpu_fbdev *vgfbdev = vgdev->vgfbdev;
struct virtio_gpu_framebuffer *fb = &vgfbdev->vgfb;
struct virtio_gpu_object *obj = gem_to_virtio_gpu_obj(fb->base.obj[0]);
bool use_dma_api = !virtio_has_iommu_quirk(vgdev->vdev);
if (use_dma_api)
dma_sync_sg_for_device(vgdev->vdev->dev.parent,
obj->pages->sgl, obj->pages->nents,
bo->pages->sgl, bo->pages->nents,
DMA_TO_DEVICE);
cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
@ -813,7 +809,7 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
cmd_p->resource_id = cpu_to_le32(resource_id);
cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
cmd_p->box = *box;
cmd_p->offset = cpu_to_le64(offset);
cmd_p->level = cpu_to_le32(level);

1
drivers/gpu/drm/vkms/vkms_crc.c
View File

@ -125,6 +125,7 @@ static uint32_t _vkms_get_crc(struct vkms_crc_data *primary_crc,
mutex_lock(&vkms_obj->pages_lock);
if (WARN_ON(!vkms_obj->vaddr)) {
mutex_unlock(&vkms_obj->pages_lock);
kfree(vaddr_out);
return crc;
}

19
drivers/gpu/drm/zte/zx_drm_drv.c
View File

@ -31,7 +31,6 @@
static const struct drm_mode_config_funcs zx_drm_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
@ -41,7 +40,6 @@ DEFINE_DRM_GEM_CMA_FOPS(zx_drm_fops);
static struct drm_driver zx_drm_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
DRIVER_ATOMIC,
.lastclose = drm_fb_helper_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = drm_gem_cma_dumb_create,
@ -101,20 +99,14 @@ static int zx_drm_bind(struct device *dev)
drm_mode_config_reset(drm);
drm_kms_helper_poll_init(drm);
ret = drm_fb_cma_fbdev_init(drm, 32, 0);
if (ret) {
DRM_DEV_ERROR(dev, "failed to init cma fbdev: %d\n", ret);
goto out_poll_fini;
}
ret = drm_dev_register(drm, 0);
if (ret)
goto out_fbdev_fini;
goto out_poll_fini;
drm_fbdev_generic_setup(drm, 32);
return 0;
out_fbdev_fini:
drm_fb_cma_fbdev_fini(drm);
out_poll_fini:
drm_kms_helper_poll_fini(drm);
drm_mode_config_cleanup(drm);
@ -131,7 +123,6 @@ static void zx_drm_unbind(struct device *dev)
struct drm_device *drm = dev_get_drvdata(dev);
drm_dev_unregister(drm);
drm_fb_cma_fbdev_fini(drm);
drm_kms_helper_poll_fini(drm);
drm_mode_config_cleanup(drm);
component_unbind_all(dev, drm);
@ -161,10 +152,8 @@ static int zx_drm_probe(struct platform_device *pdev)
if (ret)
return ret;
for_each_available_child_of_node(parent, child) {
for_each_available_child_of_node(parent, child)
component_match_add(dev, &match, compare_of, child);
of_node_put(child);
}
return component_master_add_with_match(dev, &zx_drm_master_ops, match);
}

2
include/drm/drm_fourcc.h
View File

@ -88,6 +88,8 @@ const struct drm_format_info *
drm_get_format_info(struct drm_device *dev,
const struct drm_mode_fb_cmd2 *mode_cmd);
uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth);
uint32_t drm_driver_legacy_fb_format(struct drm_device *dev,
uint32_t bpp, uint32_t depth);
int drm_format_num_planes(uint32_t format);
int drm_format_plane_cpp(uint32_t format, int plane);
int drm_format_horz_chroma_subsampling(uint32_t format);