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x86/irq: Clean up io_apic.h
Clean up io_apic.h by: 1) moving definition of struct mp_ioapic_gsi into io_apic.c 2) changing mp_pin_to_gsi() and mp_ioapic_gsi_routing() as static 3) removing unused MP_MAX_IOAPIC_PIN 4) removing useless forward declaration 5) removing useless comments Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Tested-by: Joerg Roedel <jroedel@suse.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Grant Likely <grant.likely@linaro.org> Link: http://lkml.kernel.org/r/1428978610-28986-20-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -113,9 +113,6 @@ extern int nr_ioapics;
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extern int mpc_ioapic_id(int ioapic);
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extern unsigned int mpc_ioapic_addr(int ioapic);
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extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic);
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#define MP_MAX_IOAPIC_PIN 127
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/* # of MP IRQ source entries */
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extern int mp_irq_entries;
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@ -135,6 +132,8 @@ extern int noioapicquirk;
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/* -1 if "noapic" boot option passed */
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extern int noioapicreroute;
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extern u32 gsi_top;
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extern unsigned long io_apic_irqs;
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#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
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@ -174,15 +173,8 @@ struct ioapic_domain_cfg {
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struct device_node *dev;
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};
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struct mp_ioapic_gsi{
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u32 gsi_base;
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u32 gsi_end;
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};
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extern u32 gsi_top;
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extern int mp_find_ioapic(u32 gsi);
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extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
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extern u32 mp_pin_to_gsi(int ioapic, int pin);
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extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
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struct irq_alloc_info *info);
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extern void mp_unmap_irq(int irq);
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@ -231,7 +223,6 @@ static inline int arch_early_ioapic_init(void) { return 0; }
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static inline void print_IO_APICs(void) {}
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#define gsi_top (NR_IRQS_LEGACY)
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static inline int mp_find_ioapic(u32 gsi) { return 0; }
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static inline u32 mp_pin_to_gsi(int ioapic, int pin) { return UINT_MAX; }
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static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
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struct irq_alloc_info *info)
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{
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@ -63,7 +63,6 @@
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#define for_each_ioapic_pin(idx, pin) \
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for_each_ioapic((idx)) \
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for_each_pin((idx), (pin))
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#define for_each_irq_pin(entry, head) \
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list_for_each_entry(entry, &head, list)
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@ -92,6 +91,11 @@ struct mp_chip_data {
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bool isa_irq;
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};
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struct mp_ioapic_gsi {
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u32 gsi_base;
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u32 gsi_end;
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};
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static struct ioapic {
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/*
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* # of IRQ routing registers
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@ -122,7 +126,7 @@ unsigned int mpc_ioapic_addr(int ioapic_idx)
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return ioapics[ioapic_idx].mp_config.apicaddr;
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}
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struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
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static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
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{
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return &ioapics[ioapic_idx].gsi_config;
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}
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@ -134,7 +138,7 @@ static inline int mp_ioapic_pin_count(int ioapic)
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return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
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}
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u32 mp_pin_to_gsi(int ioapic, int pin)
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static inline u32 mp_pin_to_gsi(int ioapic, int pin)
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{
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return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
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}
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@ -1153,8 +1157,7 @@ static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
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return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
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}
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int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
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struct irq_alloc_info *info)
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int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
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{
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int ioapic, pin, idx;
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@ -1719,7 +1722,6 @@ static int __init timer_irq_works(void)
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* This is not complete - we should be able to fake
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* an edge even if it isn't on the 8259A...
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*/
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static unsigned int startup_ioapic_irq(struct irq_data *data)
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{
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int was_pending = 0, irq = data->irq;
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@ -1737,15 +1739,6 @@ static unsigned int startup_ioapic_irq(struct irq_data *data)
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return was_pending;
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}
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/*
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* Level and edge triggered IO-APIC interrupts need different handling,
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* so we use two separate IRQ descriptors. Edge triggered IRQs can be
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* handled with the level-triggered descriptor, but that one has slightly
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* more overhead. Level-triggered interrupts cannot be handled with the
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* edge-triggered handler, without risking IRQ storms and other ugly
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* races.
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*/
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static void __target_IO_APIC_irq(unsigned int irq, struct irq_cfg *cfg,
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struct mp_chip_data *data)
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{
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