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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 22:36:49 +07:00
drm/amdgpu:add lock_reset for SRIOV
this lock is used for sriov_gpu_reset, only get this mutex can run into sriov_gpu_reset. we have couple source triggers gpu_reset for SRIOV: 1) submit timedout and trigger reset voluntarily 2) invalid instruction detected by ENGINE and trigger reset voluntarily 2) hypervisor found world switch hang and trigger flr and notify guest to do reset. all need take care and we need a mutex to protect the consistency of reset routine. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2351,6 +2351,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
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struct amdgpu_ring *ring;
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struct dma_fence *fence = NULL, *next = NULL;
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mutex_lock(&adev->virt.lock_reset);
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atomic_inc(&adev->gpu_reset_counter);
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/* block TTM */
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@ -2436,6 +2437,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
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dev_info(adev->dev, "GPU reset failed\n");
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}
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mutex_unlock(&adev->virt.lock_reset);
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return r;
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}
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@ -98,6 +98,7 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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adev->enable_virtual_display = true;
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mutex_init(&adev->virt.lock_kiq);
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mutex_init(&adev->virt.lock_reset);
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}
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uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
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@ -47,6 +47,7 @@ struct amdgpu_virt {
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bool chained_ib_support;
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uint32_t reg_val_offs;
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struct mutex lock_kiq;
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struct mutex lock_reset;
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struct amdgpu_irq_src ack_irq;
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struct amdgpu_irq_src rcv_irq;
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struct delayed_work flr_work;
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