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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Staging: et131x: Bring tx into coding style
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
fb034f841d
commit
1458d82b45
@ -133,7 +133,8 @@ int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
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(struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
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&tx_ring->tx_desc_ring_pa);
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if (!adapter->tx_ring.tx_desc_ring) {
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dev_err(&adapter->pdev->dev, "Cannot alloc memory for Tx Ring\n");
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dev_err(&adapter->pdev->dev,
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"Cannot alloc memory for Tx Ring\n");
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return -ENOMEM;
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}
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@ -169,7 +170,7 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
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if (adapter->tx_ring.tx_desc_ring) {
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/* Free memory relating to Tx rings here */
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desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
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+ 4096 - 1;
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+ 4096 - 1;
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pci_free_consistent(adapter->pdev,
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desc_size,
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adapter->tx_ring.tx_desc_ring,
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@ -193,6 +194,9 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
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/**
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* ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
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* @etdev: pointer to our private adapter structure
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*
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* Configure the transmit engine with the ring buffers we have created
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* and prepare it for use.
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*/
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void ConfigTxDmaRegs(struct et131x_adapter *etdev)
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{
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@ -265,11 +269,11 @@ void et131x_init_send(struct et131x_adapter *adapter)
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/* Go through and set up each TCB */
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for (ct = 0; ct++ < NUM_TCB; tcb++)
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/* Set the link pointer in HW TCB to the next TCB in the
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* chain. If this is the last TCB in the chain, also set the
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* tail pointer.
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* chain
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*/
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tcb->next = tcb + 1;
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/* Set the tail pointer */
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tcb--;
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tx_ring->tcb_qtail = tcb;
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tcb->next = NULL;
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@ -370,7 +374,7 @@ static int et131x_send_packet(struct sk_buff *skb,
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tcb->skb = skb;
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if ((skb->data != NULL) && ((skb->len - skb->data_len) >= 6)) {
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if (skb->data != NULL && skb->len - skb->data_len >= 6) {
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shbufva = (u16 *) skb->data;
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if ((shbufva[0] == 0xffff) &&
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@ -389,12 +393,11 @@ static int et131x_send_packet(struct sk_buff *skb,
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if (status != 0) {
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spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
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if (etdev->tx_ring.tcb_qtail) {
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if (etdev->tx_ring.tcb_qtail)
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etdev->tx_ring.tcb_qtail->next = tcb;
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} else {
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else
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/* Apparently ready Q is empty. */
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etdev->tx_ring.tcb_qhead = tcb;
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}
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etdev->tx_ring.tcb_qtail = tcb;
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spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
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@ -535,9 +538,8 @@ static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
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return -EIO;
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if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
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if (++etdev->tx_ring.since_irq ==
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PARM_TX_NUM_BUFS_DEF) {
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/* Last element & Interrupt flag */
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if (++etdev->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
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/* Last element & Interrupt flag */
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desc[frag - 1].flags = 0x5;
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etdev->tx_ring.since_irq = 0;
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} else { /* Last element */
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@ -569,10 +571,10 @@ static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
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add_10bit(&etdev->tx_ring.send_idx, thiscopy);
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if (INDEX10(etdev->tx_ring.send_idx)== 0 ||
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INDEX10(etdev->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
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etdev->tx_ring.send_idx &= ~ET_DMA10_MASK;
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etdev->tx_ring.send_idx ^= ET_DMA10_WRAP;
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if (INDEX10(etdev->tx_ring.send_idx) == 0 ||
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INDEX10(etdev->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
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etdev->tx_ring.send_idx &= ~ET_DMA10_MASK;
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etdev->tx_ring.send_idx ^= ET_DMA10_WRAP;
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}
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if (remainder) {
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@ -587,7 +589,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
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if (etdev->tx_ring.send_idx)
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tcb->index = NUM_DESC_PER_RING_TX - 1;
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else
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tcb->index= ET_DMA10_WRAP | (NUM_DESC_PER_RING_TX - 1);
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tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
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} else
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tcb->index = etdev->tx_ring.send_idx - 1;
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@ -653,8 +655,8 @@ inline void et131x_free_send_packet(struct et131x_adapter *etdev,
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* they point to
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*/
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do {
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desc =(struct tx_desc *) (etdev->tx_ring.tx_desc_ring +
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INDEX10(tcb->index_start));
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desc = (struct tx_desc *)(etdev->tx_ring.tx_desc_ring +
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INDEX10(tcb->index_start));
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pci_unmap_single(etdev->pdev,
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desc->addr_lo,
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@ -662,9 +664,9 @@ inline void et131x_free_send_packet(struct et131x_adapter *etdev,
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add_10bit(&tcb->index_start, 1);
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if (INDEX10(tcb->index_start) >=
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NUM_DESC_PER_RING_TX) {
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tcb->index_start &= ~ET_DMA10_MASK;
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tcb->index_start ^= ET_DMA10_WRAP;
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NUM_DESC_PER_RING_TX) {
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tcb->index_start &= ~ET_DMA10_MASK;
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tcb->index_start ^= ET_DMA10_WRAP;
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}
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} while (desc != (etdev->tx_ring.tx_desc_ring +
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INDEX10(tcb->index)));
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@ -708,7 +710,7 @@ void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
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tcb = etdev->tx_ring.send_head;
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while ((tcb != NULL) && (freed < NUM_TCB)) {
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while (tcb != NULL && freed < NUM_TCB) {
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struct tcb *next = tcb->next;
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etdev->tx_ring.send_head = next;
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@ -748,7 +750,7 @@ void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
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{
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unsigned long flags;
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u32 serviced;
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struct tcb * tcb;
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struct tcb *tcb;
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u32 index;
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serviced = readl(&etdev->regs->txdma.NewServiceComplete);
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@ -793,7 +795,7 @@ void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
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}
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/* Wake up the queue when we hit a low-water mark */
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if (etdev->tx_ring.used <= (NUM_TCB / 3))
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if (etdev->tx_ring.used <= NUM_TCB / 3)
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netif_wake_queue(etdev->netdev);
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spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
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@ -126,7 +126,7 @@ struct tx_ring {
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* three of these (including used) are controlled via the
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* TCBSendQLock. This lock should be secured prior to incementing /
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* decrementing used, or any queue manipulation on send_head /
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* Tail
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* tail
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*/
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struct tcb *send_head;
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struct tcb *send_tail;
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@ -136,7 +136,7 @@ struct tx_ring {
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struct tx_desc *tx_desc_ring;
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dma_addr_t tx_desc_ring_pa;
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/* ReadyToSend indicates where we last wrote to in the descriptor ring. */
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/* send_idx indicates where we last wrote to in the descriptor ring. */
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u32 send_idx;
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/* The location of the write-back status block */
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