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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 13:46:42 +07:00
iwl3945: kill iwl3945_rx_queue_restock
This patch kills iwl3945_rx_queue_restock function on prise of new hw_params.rx_wrt_ptr_reg which holds per NIC RX write pointer register. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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f5965955e0
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141c43a3e4
@ -1218,7 +1218,7 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
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/* Look at using this instead:
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rxq->need_update = 1;
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iwl3945_rx_queue_update_write_ptr(priv, rxq);
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iwl_rx_queue_update_write_ptr(priv, rxq);
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*/
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rc = iwl_grab_nic_access(priv);
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@ -2492,6 +2492,8 @@ int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
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priv->hw_params.max_stations = IWL3945_STATION_COUNT;
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priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
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priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
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return 0;
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}
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@ -225,8 +225,6 @@ extern int __must_check iwl3945_send_cmd(struct iwl_priv *priv,
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struct iwl_host_cmd *cmd);
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extern unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
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struct ieee80211_hdr *hdr,int left);
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extern int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv,
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struct iwl_rx_queue *q);
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extern int iwl3945_send_statistics_request(struct iwl_priv *priv);
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extern void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
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u32 decrypt_res,
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@ -822,6 +822,8 @@ static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
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priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
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priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
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priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
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priv->hw_params.tx_chains_num = 2;
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priv->hw_params.rx_chains_num = 2;
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priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
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@ -844,6 +844,8 @@ static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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priv->hw_params.max_bsm_size = 0;
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priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
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BIT(IEEE80211_BAND_5GHZ);
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priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
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priv->hw_params.sens = &iwl5000_sensitivity;
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switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
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@ -563,6 +563,7 @@ struct iwl_sensitivity_ranges {
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* @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
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* @max_rxq_log: Log-base-2 of max_rxq_size
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* @rx_buf_size: Rx buffer size
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* @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
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* @max_stations:
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* @bcast_sta_id:
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* @fat_channel: is 40MHz width possible in band 2.4
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@ -584,6 +585,7 @@ struct iwl_hw_params {
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u16 max_rxq_size;
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u16 max_rxq_log;
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u32 rx_buf_size;
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u32 rx_wrt_ptr_reg;
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u32 max_pkt_size;
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u8 max_stations;
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u8 bcast_sta_id;
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@ -125,9 +125,10 @@ EXPORT_SYMBOL(iwl_rx_queue_space);
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*/
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int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
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{
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u32 reg = 0;
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int ret = 0;
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unsigned long flags;
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u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg;
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u32 reg;
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int ret = 0;
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spin_lock_irqsave(&q->lock, flags);
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@ -149,15 +150,14 @@ int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
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goto exit_unlock;
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/* Device expects a multiple of 8 */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
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q->write & ~0x7);
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iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write & ~0x7);
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iwl_release_nic_access(priv);
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/* Else device is assumed to be awake */
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} else
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} else {
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/* Device expects a multiple of 8 */
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iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
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iwl_write32(priv, rx_wrt_ptr_reg, q->write & ~0x7);
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}
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q->need_update = 0;
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@ -3218,52 +3218,6 @@ static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
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return s;
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}
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/**
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* iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
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*/
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int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
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{
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u32 reg = 0;
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int rc = 0;
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unsigned long flags;
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spin_lock_irqsave(&q->lock, flags);
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if (q->need_update == 0)
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goto exit_unlock;
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/* If power-saving is in use, make sure device is awake */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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goto exit_unlock;
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}
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rc = iwl_grab_nic_access(priv);
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if (rc)
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goto exit_unlock;
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/* Device expects a multiple of 8 */
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iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
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q->write & ~0x7);
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iwl_release_nic_access(priv);
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/* Else device is assumed to be awake */
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} else
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/* Device expects a multiple of 8 */
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iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
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q->need_update = 0;
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exit_unlock:
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spin_unlock_irqrestore(&q->lock, flags);
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return rc;
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}
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/**
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* iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
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*/
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@ -3320,7 +3274,7 @@ static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
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spin_lock_irqsave(&rxq->lock, flags);
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rxq->need_update = 1;
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spin_unlock_irqrestore(&rxq->lock, flags);
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rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
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rc = iwl_rx_queue_update_write_ptr(priv, rxq);
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if (rc)
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return rc;
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}
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@ -4007,7 +3961,7 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
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/* uCode wakes up after power-down sleep */
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if (inta & CSR_INT_BIT_WAKEUP) {
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IWL_DEBUG_ISR("Wakeup interrupt\n");
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iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
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iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
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iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
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iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
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iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
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