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synced 2024-12-02 16:26:38 +07:00
sky2: fix hang on shutdown (and other irq issues)
There are several problems with recent change to how IRQ's are setup. * synchronize_irq in sky2_shutdown would hang because there was no IRQ setup. * when device was set to down, some IRQ bits left enabled so a hardware error would produce IRQ with no handler * quick link on Optima chip set was enabled without handler * suspend/resume would leave IRQ on with no handler if device was down Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1747,6 +1747,11 @@ static int sky2_up(struct net_device *dev)
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sky2_hw_up(sky2);
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if (hw->chip_id == CHIP_ID_YUKON_OPT ||
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hw->chip_id == CHIP_ID_YUKON_PRM ||
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hw->chip_id == CHIP_ID_YUKON_OP_2)
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imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
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/* Enable interrupts from phy/mac for port */
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imask = sky2_read32(hw, B0_IMSK);
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imask |= portirq_msk[port];
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@ -2101,15 +2106,21 @@ static int sky2_down(struct net_device *dev)
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netif_info(sky2, ifdown, dev, "disabling interface\n");
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/* Disable port IRQ */
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sky2_write32(hw, B0_IMSK,
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sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
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sky2_read32(hw, B0_IMSK);
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if (hw->ports == 1) {
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sky2_write32(hw, B0_IMSK, 0);
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sky2_read32(hw, B0_IMSK);
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napi_disable(&hw->napi);
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free_irq(hw->pdev->irq, hw);
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} else {
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u32 imask;
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/* Disable port IRQ */
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imask = sky2_read32(hw, B0_IMSK);
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imask &= ~portirq_msk[sky2->port];
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sky2_write32(hw, B0_IMSK, imask);
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sky2_read32(hw, B0_IMSK);
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synchronize_irq(hw->pdev->irq);
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napi_synchronize(&hw->napi);
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}
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@ -3258,7 +3269,6 @@ static void sky2_reset(struct sky2_hw *hw)
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hw->chip_id == CHIP_ID_YUKON_PRM ||
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hw->chip_id == CHIP_ID_YUKON_OP_2) {
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u16 reg;
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u32 msk;
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if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
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/* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
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@ -3281,11 +3291,6 @@ static void sky2_reset(struct sky2_hw *hw)
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
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/* enable PHY Quick Link */
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msk = sky2_read32(hw, B0_IMSK);
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msk |= Y2_IS_PHY_QLNK;
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sky2_write32(hw, B0_IMSK, msk);
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/* check if PSMv2 was running before */
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reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
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if (reg & PCI_EXP_LNKCTL_ASPMC)
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@ -3412,7 +3417,9 @@ static void sky2_all_down(struct sky2_hw *hw)
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sky2_read32(hw, B0_IMSK);
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sky2_write32(hw, B0_IMSK, 0);
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synchronize_irq(hw->pdev->irq);
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if (hw->ports > 1 || netif_running(hw->dev[0]))
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synchronize_irq(hw->pdev->irq);
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napi_disable(&hw->napi);
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for (i = 0; i < hw->ports; i++) {
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@ -3430,7 +3437,7 @@ static void sky2_all_down(struct sky2_hw *hw)
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static void sky2_all_up(struct sky2_hw *hw)
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{
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u32 imask = Y2_IS_BASE;
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u32 imask = 0;
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int i;
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for (i = 0; i < hw->ports; i++) {
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@ -3446,11 +3453,13 @@ static void sky2_all_up(struct sky2_hw *hw)
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netif_wake_queue(dev);
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}
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sky2_write32(hw, B0_IMSK, imask);
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sky2_read32(hw, B0_IMSK);
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sky2_read32(hw, B0_Y2_SP_LISR);
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napi_enable(&hw->napi);
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if (imask || hw->ports > 1) {
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imask |= Y2_IS_BASE;
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sky2_write32(hw, B0_IMSK, imask);
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sky2_read32(hw, B0_IMSK);
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sky2_read32(hw, B0_Y2_SP_LISR);
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napi_enable(&hw->napi);
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}
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}
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static void sky2_restart(struct work_struct *work)
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