mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e1000: Elementary checkpatch warnings and checks removed
Signed-off-by: Janusz Wolak <januszvdm@gmail.com> Acked-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Janusz Wolak
Jeff Kirsher
parent
c619581a79
commit
13a87c124e
@ -1,5 +1,5 @@
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/*******************************************************************************
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*
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2006 Intel Corporation.
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@ -624,8 +624,8 @@ s32 e1000_init_hw(struct e1000_hw *hw)
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/* Workaround for PCI-X problem when BIOS sets MMRBC
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* incorrectly.
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*/
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if (hw->bus_type == e1000_bus_type_pcix
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&& e1000_pcix_get_mmrbc(hw) > 2048)
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if (hw->bus_type == e1000_bus_type_pcix &&
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e1000_pcix_get_mmrbc(hw) > 2048)
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e1000_pcix_set_mmrbc(hw, 2048);
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break;
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}
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@ -684,9 +684,8 @@ static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
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ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
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&eeprom_data);
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if (ret_val) {
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if (ret_val)
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return ret_val;
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}
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if (eeprom_data != EEPROM_RESERVED_WORD) {
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/* Adjust SERDES output amplitude only. */
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@ -1074,8 +1073,8 @@ static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
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if (hw->mac_type <= e1000_82543 ||
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hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
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hw->mac_type == e1000_82541_rev_2
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|| hw->mac_type == e1000_82547_rev_2)
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hw->mac_type == e1000_82541_rev_2 ||
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hw->mac_type == e1000_82547_rev_2)
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hw->phy_reset_disable = false;
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return E1000_SUCCESS;
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@ -1881,10 +1880,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
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&& (!hw->autoneg)
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&& (hw->forced_speed_duplex == e1000_10_full
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|| hw->forced_speed_duplex == e1000_10_half)) {
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if ((hw->mac_type == e1000_82544 ||
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hw->mac_type == e1000_82543) &&
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(!hw->autoneg) &&
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(hw->forced_speed_duplex == e1000_10_full ||
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hw->forced_speed_duplex == e1000_10_half)) {
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ret_val = e1000_polarity_reversal_workaround(hw);
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if (ret_val)
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return ret_val;
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@ -2084,11 +2084,12 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
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* so we had to force link. In this case, we need to force the
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* configuration of the MAC to match the "fc" parameter.
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*/
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if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
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|| ((hw->media_type == e1000_media_type_internal_serdes)
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&& (hw->autoneg_failed))
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|| ((hw->media_type == e1000_media_type_copper)
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&& (!hw->autoneg))) {
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if (((hw->media_type == e1000_media_type_fiber) &&
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(hw->autoneg_failed)) ||
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((hw->media_type == e1000_media_type_internal_serdes) &&
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(hw->autoneg_failed)) ||
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((hw->media_type == e1000_media_type_copper) &&
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(!hw->autoneg))) {
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ret_val = e1000_force_mac_fc(hw);
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if (ret_val) {
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e_dbg("Error forcing flow control settings\n");
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@ -2458,10 +2459,11 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
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* happen due to the execution of this workaround.
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*/
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if ((hw->mac_type == e1000_82544
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|| hw->mac_type == e1000_82543) && (!hw->autoneg)
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&& (hw->forced_speed_duplex == e1000_10_full
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|| hw->forced_speed_duplex == e1000_10_half)) {
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if ((hw->mac_type == e1000_82544 ||
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hw->mac_type == e1000_82543) &&
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(!hw->autoneg) &&
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(hw->forced_speed_duplex == e1000_10_full ||
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hw->forced_speed_duplex == e1000_10_half)) {
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ew32(IMC, 0xffffffff);
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ret_val =
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e1000_polarity_reversal_workaround(hw);
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@ -2526,8 +2528,10 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
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*/
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if (hw->tbi_compatibility_en) {
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u16 speed, duplex;
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ret_val =
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e1000_get_speed_and_duplex(hw, &speed, &duplex);
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if (ret_val) {
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e_dbg
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("Error getting link speed and duplex\n");
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@ -2626,10 +2630,10 @@ s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
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e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
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if (ret_val)
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return ret_val;
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if ((*speed == SPEED_100
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&& !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
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|| (*speed == SPEED_10
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&& !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
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if ((*speed == SPEED_100 &&
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!(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
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(*speed == SPEED_10 &&
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!(phy_data & NWAY_LPAR_10T_FD_CAPS)))
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*duplex = HALF_DUPLEX;
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}
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}
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@ -2662,9 +2666,9 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw)
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ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
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if (ret_val)
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return ret_val;
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if (phy_data & MII_SR_AUTONEG_COMPLETE) {
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if (phy_data & MII_SR_AUTONEG_COMPLETE)
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return E1000_SUCCESS;
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}
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msleep(100);
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}
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return E1000_SUCCESS;
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@ -2801,7 +2805,6 @@ static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
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return data;
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}
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/**
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* e1000_read_phy_reg - read a phy register
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* @hw: Struct containing variables accessed by shared code
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@ -2879,7 +2882,7 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
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e_dbg("MDI Read Error\n");
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return -E1000_ERR_PHY;
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}
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*phy_data = (u16) mdic;
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*phy_data = (u16)mdic;
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} else {
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mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
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(phy_addr << E1000_MDIC_PHY_SHIFT) |
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@ -2904,7 +2907,7 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
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e_dbg("MDI Error\n");
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return -E1000_ERR_PHY;
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}
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*phy_data = (u16) mdic;
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*phy_data = (u16)mdic;
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}
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} else {
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/* We must first send a preamble through the MDIO pin to signal
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@ -2958,7 +2961,7 @@ s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
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if ((hw->phy_type == e1000_phy_igp) &&
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(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
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ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
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(u16) reg_addr);
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(u16)reg_addr);
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if (ret_val) {
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spin_unlock_irqrestore(&e1000_phy_lock, flags);
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return ret_val;
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@ -2991,7 +2994,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
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* the desired data.
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*/
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if (hw->mac_type == e1000_ce4100) {
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mdic = (((u32) phy_data) |
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mdic = (((u32)phy_data) |
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(reg_addr << E1000_MDIC_REG_SHIFT) |
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(phy_addr << E1000_MDIC_PHY_SHIFT) |
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(INTEL_CE_GBE_MDIC_OP_WRITE) |
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@ -3013,7 +3016,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
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return -E1000_ERR_PHY;
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}
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} else {
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mdic = (((u32) phy_data) |
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mdic = (((u32)phy_data) |
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(reg_addr << E1000_MDIC_REG_SHIFT) |
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(phy_addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_WRITE));
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@ -3051,7 +3054,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
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mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
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(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
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mdic <<= 16;
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mdic |= (u32) phy_data;
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mdic |= (u32)phy_data;
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e1000_shift_out_mdi_bits(hw, mdic, 32);
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}
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@ -3174,14 +3177,14 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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hw->phy_id = (u32) (phy_id_high << 16);
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hw->phy_id = (u32)(phy_id_high << 16);
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udelay(20);
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ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
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if (ret_val)
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return ret_val;
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hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
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hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
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hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
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hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
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switch (hw->mac_type) {
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case e1000_82543:
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@ -3399,7 +3402,6 @@ static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
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phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
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SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
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e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
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}
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return E1000_SUCCESS;
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@ -3609,11 +3611,11 @@ static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
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*/
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mask = 0x01 << (count - 1);
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eecd = er32(EECD);
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if (eeprom->type == e1000_eeprom_microwire) {
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if (eeprom->type == e1000_eeprom_microwire)
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eecd &= ~E1000_EECD_DO;
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} else if (eeprom->type == e1000_eeprom_spi) {
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else if (eeprom->type == e1000_eeprom_spi)
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eecd |= E1000_EECD_DO;
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}
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do {
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/* A "1" is shifted out to the EEPROM by setting bit "DI" to a
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* "1", and then raising and then lowering the clock (the SK bit
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@ -3849,7 +3851,7 @@ static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
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do {
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e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
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hw->eeprom.opcode_bits);
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spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
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spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
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if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
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break;
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@ -3880,6 +3882,7 @@ static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
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s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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{
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s32 ret;
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mutex_lock(&e1000_eeprom_lock);
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ret = e1000_do_read_eeprom(hw, offset, words, data);
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mutex_unlock(&e1000_eeprom_lock);
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@ -3901,8 +3904,9 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
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/* A check for invalid values: offset too large, too many words, and
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* not enough words.
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*/
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if ((offset >= eeprom->word_size)
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|| (words > eeprom->word_size - offset) || (words == 0)) {
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if ((offset >= eeprom->word_size) ||
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(words > eeprom->word_size - offset) ||
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(words == 0)) {
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e_dbg("\"words\" parameter out of bounds. Words = %d,"
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"size = %d\n", offset, eeprom->word_size);
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return -E1000_ERR_EEPROM;
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@ -3938,7 +3942,7 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
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/* Send the READ command (opcode + addr) */
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e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
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e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
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e1000_shift_out_ee_bits(hw, (u16)(offset * 2),
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eeprom->address_bits);
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/* Read the data. The address of the eeprom internally
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@ -3958,7 +3962,7 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
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e1000_shift_out_ee_bits(hw,
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EEPROM_READ_OPCODE_MICROWIRE,
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eeprom->opcode_bits);
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e1000_shift_out_ee_bits(hw, (u16) (offset + i),
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e1000_shift_out_ee_bits(hw, (u16)(offset + i),
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eeprom->address_bits);
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/* Read the data. For microwire, each word requires the
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@ -4003,7 +4007,7 @@ s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
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return E1000_SUCCESS;
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#endif
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if (checksum == (u16) EEPROM_SUM)
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if (checksum == (u16)EEPROM_SUM)
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return E1000_SUCCESS;
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else {
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e_dbg("EEPROM Checksum Invalid\n");
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@ -4030,7 +4034,7 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
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}
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checksum += eeprom_data;
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}
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checksum = (u16) EEPROM_SUM - checksum;
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checksum = (u16)EEPROM_SUM - checksum;
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if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
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e_dbg("EEPROM Write Error\n");
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return -E1000_ERR_EEPROM;
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@ -4051,6 +4055,7 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
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s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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{
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s32 ret;
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mutex_lock(&e1000_eeprom_lock);
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ret = e1000_do_write_eeprom(hw, offset, words, data);
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mutex_unlock(&e1000_eeprom_lock);
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@ -4072,8 +4077,9 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
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/* A check for invalid values: offset too large, too many words, and
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* not enough words.
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*/
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if ((offset >= eeprom->word_size)
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|| (words > eeprom->word_size - offset) || (words == 0)) {
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if ((offset >= eeprom->word_size) ||
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(words > eeprom->word_size - offset) ||
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(words == 0)) {
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e_dbg("\"words\" parameter out of bounds\n");
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return -E1000_ERR_EEPROM;
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}
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@ -4132,7 +4138,7 @@ static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
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/* Send the Write command (8-bit opcode + addr) */
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e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
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e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
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e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),
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eeprom->address_bits);
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/* Send the data */
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@ -4142,6 +4148,7 @@ static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
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*/
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while (widx < words) {
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u16 word_out = data[widx];
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word_out = (word_out >> 8) | (word_out << 8);
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e1000_shift_out_ee_bits(hw, word_out, 16);
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widx++;
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@ -4183,9 +4190,9 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
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* EEPROM into write/erase mode.
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*/
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e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
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(u16) (eeprom->opcode_bits + 2));
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(u16)(eeprom->opcode_bits + 2));
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e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
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e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
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/* Prepare the EEPROM */
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e1000_standby_eeprom(hw);
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@ -4195,7 +4202,7 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
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e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
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eeprom->opcode_bits);
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e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
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e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
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eeprom->address_bits);
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/* Send the data */
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@ -4236,9 +4243,9 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
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* EEPROM out of write/erase mode.
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*/
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e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
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(u16) (eeprom->opcode_bits + 2));
|
||||
(u16)(eeprom->opcode_bits + 2));
|
||||
|
||||
e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
|
||||
e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
|
||||
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
@ -4261,8 +4268,8 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw)
|
||||
e_dbg("EEPROM Read Error\n");
|
||||
return -E1000_ERR_EEPROM;
|
||||
}
|
||||
hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
|
||||
hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
|
||||
hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
|
||||
hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);
|
||||
}
|
||||
|
||||
switch (hw->mac_type) {
|
||||
@ -4329,19 +4336,19 @@ u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
|
||||
*/
|
||||
case 0:
|
||||
/* [47:36] i.e. 0x563 for above example address */
|
||||
hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
|
||||
hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
|
||||
break;
|
||||
case 1:
|
||||
/* [46:35] i.e. 0xAC6 for above example address */
|
||||
hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
|
||||
hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
|
||||
break;
|
||||
case 2:
|
||||
/* [45:34] i.e. 0x5D8 for above example address */
|
||||
hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
|
||||
hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
|
||||
break;
|
||||
case 3:
|
||||
/* [43:32] i.e. 0x634 for above example address */
|
||||
hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
|
||||
hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
|
||||
break;
|
||||
}
|
||||
|
||||
@ -4362,9 +4369,9 @@ void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
|
||||
/* HW expects these in little endian so we reverse the byte order
|
||||
* from network order (big endian) to little endian
|
||||
*/
|
||||
rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
|
||||
((u32) addr[2] << 16) | ((u32) addr[3] << 24));
|
||||
rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
|
||||
rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
|
||||
((u32)addr[2] << 16) | ((u32)addr[3] << 24));
|
||||
rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
|
||||
|
||||
/* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
|
||||
* unit hang.
|
||||
@ -4538,7 +4545,7 @@ s32 e1000_setup_led(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
|
||||
(u16) (hw->phy_spd_default &
|
||||
(u16)(hw->phy_spd_default &
|
||||
~IGP01E1000_GMII_SPD));
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
@ -4803,7 +4810,7 @@ void e1000_reset_adaptive(struct e1000_hw *hw)
|
||||
void e1000_update_adaptive(struct e1000_hw *hw)
|
||||
{
|
||||
if (hw->adaptive_ifs) {
|
||||
if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
|
||||
if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
|
||||
if (hw->tx_packet_delta > MIN_NUM_XMITS) {
|
||||
hw->in_ifs_mode = true;
|
||||
if (hw->current_ifs_val < hw->ifs_max_val) {
|
||||
@ -4817,8 +4824,8 @@ void e1000_update_adaptive(struct e1000_hw *hw)
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (hw->in_ifs_mode
|
||||
&& (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
|
||||
if (hw->in_ifs_mode &&
|
||||
(hw->tx_packet_delta <= MIN_NUM_XMITS)) {
|
||||
hw->current_ifs_val = 0;
|
||||
hw->in_ifs_mode = false;
|
||||
ew32(AIT, 0);
|
||||
@ -4923,7 +4930,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
|
||||
|
||||
/* Use old method for Phy older than IGP */
|
||||
if (hw->phy_type == e1000_phy_m88) {
|
||||
|
||||
ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
|
||||
&phy_data);
|
||||
if (ret_val)
|
||||
@ -4967,7 +4973,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
|
||||
};
|
||||
/* Read the AGC registers for all channels */
|
||||
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
|
||||
|
||||
ret_val =
|
||||
e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
|
||||
if (ret_val)
|
||||
@ -4977,8 +4982,8 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
|
||||
|
||||
/* Value bound check. */
|
||||
if ((cur_agc_value >=
|
||||
IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
|
||||
|| (cur_agc_value == 0))
|
||||
IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
|
||||
(cur_agc_value == 0))
|
||||
return -E1000_ERR_PHY;
|
||||
|
||||
agc_value += cur_agc_value;
|
||||
@ -5055,7 +5060,6 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
|
||||
*/
|
||||
if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
|
||||
IGP01E1000_PSSR_SPEED_1000MBPS) {
|
||||
|
||||
/* Read the GIG initialization PCS register (0x00B4) */
|
||||
ret_val =
|
||||
e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
|
||||
@ -5176,8 +5180,8 @@ static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
|
||||
hw->ffe_config_state = e1000_ffe_config_active;
|
||||
|
||||
ret_val = e1000_write_phy_reg(hw,
|
||||
IGP01E1000_PHY_DSP_FFE,
|
||||
IGP01E1000_PHY_DSP_FFE_CM_CP);
|
||||
IGP01E1000_PHY_DSP_FFE,
|
||||
IGP01E1000_PHY_DSP_FFE_CM_CP);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
break;
|
||||
@ -5244,7 +5248,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
|
||||
msleep(20);
|
||||
|
||||
ret_val = e1000_write_phy_reg(hw, 0x0000,
|
||||
IGP01E1000_IEEE_FORCE_GIGA);
|
||||
IGP01E1000_IEEE_FORCE_GIGA);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
|
||||
@ -5265,7 +5269,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
|
||||
}
|
||||
|
||||
ret_val = e1000_write_phy_reg(hw, 0x0000,
|
||||
IGP01E1000_IEEE_RESTART_AUTONEG);
|
||||
IGP01E1000_IEEE_RESTART_AUTONEG);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
@ -5300,7 +5304,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
|
||||
msleep(20);
|
||||
|
||||
ret_val = e1000_write_phy_reg(hw, 0x0000,
|
||||
IGP01E1000_IEEE_FORCE_GIGA);
|
||||
IGP01E1000_IEEE_FORCE_GIGA);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
ret_val =
|
||||
@ -5310,7 +5314,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
|
||||
return ret_val;
|
||||
|
||||
ret_val = e1000_write_phy_reg(hw, 0x0000,
|
||||
IGP01E1000_IEEE_RESTART_AUTONEG);
|
||||
IGP01E1000_IEEE_RESTART_AUTONEG);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
@ -5347,9 +5351,8 @@ static s32 e1000_set_phy_mode(struct e1000_hw *hw)
|
||||
ret_val =
|
||||
e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
|
||||
&eeprom_data);
|
||||
if (ret_val) {
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
if ((eeprom_data != EEPROM_RESERVED_WORD) &&
|
||||
(eeprom_data & EEPROM_PHY_CLASS_A)) {
|
||||
@ -5396,8 +5399,8 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
|
||||
* from the lowest speeds starting from 10Mbps. The capability is used
|
||||
* for Dx transitions and states
|
||||
*/
|
||||
if (hw->mac_type == e1000_82541_rev_2
|
||||
|| hw->mac_type == e1000_82547_rev_2) {
|
||||
if (hw->mac_type == e1000_82541_rev_2 ||
|
||||
hw->mac_type == e1000_82547_rev_2) {
|
||||
ret_val =
|
||||
e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
|
||||
if (ret_val)
|
||||
@ -5447,11 +5450,9 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
}
|
||||
} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
|
||||
|| (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
|
||||
|| (hw->autoneg_advertised ==
|
||||
AUTONEG_ADVERTISE_10_100_ALL)) {
|
||||
|
||||
} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
|
||||
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
|
||||
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
|
||||
if (hw->mac_type == e1000_82541_rev_2 ||
|
||||
hw->mac_type == e1000_82547_rev_2) {
|
||||
phy_data |= IGP01E1000_GMII_FLEX_SPD;
|
||||
@ -5475,7 +5476,6 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
|
||||
phy_data);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
}
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
@ -5543,7 +5543,6 @@ static s32 e1000_set_vco_speed(struct e1000_hw *hw)
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* e1000_enable_mng_pass_thru - check for bmc pass through
|
||||
* @hw: Struct containing variables accessed by shared code
|
||||
|
||||
Loading…
Reference in New Issue
Block a user