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drm/amd/display: add odm visual confirm

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[why]
Hard to determine if pipe combine is done with MPC or ODM

[how]
Add new visual confirm type, this will mark each MPCC tree
with a different color

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jun Lei 2019-09-25 09:46:38 -04:00 committed by Alex Deucher
parent 4294f72219
commit 123c53a97a
3 changed files with 29 additions and 1 deletions
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1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -229,6 +229,7 @@ enum visual_confirm {
VISUAL_CONFIRM_DISABLE = 0, VISUAL_CONFIRM_DISABLE = 0,
VISUAL_CONFIRM_SURFACE = 1, VISUAL_CONFIRM_SURFACE = 1,
VISUAL_CONFIRM_HDR = 2, VISUAL_CONFIRM_HDR = 2,
VISUAL_CONFIRM_MPCTREE = 4,
}; };
enum dcc_option { enum dcc_option {

25
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -1996,6 +1996,28 @@ static void dcn20_reset_hw_ctx_wrap(
} }
} }
void dcn20_get_mpctree_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color)
{
const struct tg_color pipe_colors[6] = {
{MAX_TG_COLOR_VALUE, 0, 0}, // red
{MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
{0, MAX_TG_COLOR_VALUE, 0}, // blue
{MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
{0, 0, MAX_TG_COLOR_VALUE}, // green
{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
};
struct pipe_ctx *top_pipe = pipe_ctx;
while (top_pipe->top_pipe) {
top_pipe = top_pipe->top_pipe;
}
*color = pipe_colors[top_pipe->pipe_idx];
}
static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
{ {
struct hubp *hubp = pipe_ctx->plane_res.hubp; struct hubp *hubp = pipe_ctx->plane_res.hubp;
@ -2013,6 +2035,9 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
dcn10_get_surface_visual_confirm_color( dcn10_get_surface_visual_confirm_color(
pipe_ctx, &blnd_cfg.black_color); pipe_ctx, &blnd_cfg.black_color);
} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
dcn20_get_mpctree_visual_confirm_color(
pipe_ctx, &blnd_cfg.black_color);
} }
if (per_pixel_alpha) if (per_pixel_alpha)

4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
View File

@ -109,5 +109,7 @@ bool dcn20_set_blend_lut(
struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
bool dcn20_set_shaper_3dlut( bool dcn20_set_shaper_3dlut(
struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
void dcn20_get_mpctree_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
#endif /* __DC_HWSS_DCN20_H__ */ #endif /* __DC_HWSS_DCN20_H__ */