mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 12:16:42 +07:00
net: emaclite: Do not use microblaze and ppc IO functions
Emaclite can be used on ARM zynq where in_be32/out_be32 IO functions are not present. Use standard __raw_readl/__raw_writel IO functions instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
3fb99fa7c7
commit
123c1407af
@ -159,34 +159,32 @@ static void xemaclite_enable_interrupts(struct net_local *drvdata)
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u32 reg_data;
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u32 reg_data;
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/* Enable the Tx interrupts for the first Buffer */
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/* Enable the Tx interrupts for the first Buffer */
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reg_data = in_be32(drvdata->base_addr + XEL_TSR_OFFSET);
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reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
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out_be32(drvdata->base_addr + XEL_TSR_OFFSET,
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__raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
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reg_data | XEL_TSR_XMIT_IE_MASK);
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drvdata->base_addr + XEL_TSR_OFFSET);
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/* Enable the Tx interrupts for the second Buffer if
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/* Enable the Tx interrupts for the second Buffer if
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* configured in HW */
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* configured in HW */
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if (drvdata->tx_ping_pong != 0) {
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if (drvdata->tx_ping_pong != 0) {
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reg_data = in_be32(drvdata->base_addr +
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reg_data = __raw_readl(drvdata->base_addr +
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XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
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__raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
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XEL_TSR_OFFSET,
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drvdata->base_addr + XEL_BUFFER_OFFSET +
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reg_data | XEL_TSR_XMIT_IE_MASK);
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XEL_TSR_OFFSET);
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}
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}
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/* Enable the Rx interrupts for the first buffer */
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/* Enable the Rx interrupts for the first buffer */
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out_be32(drvdata->base_addr + XEL_RSR_OFFSET,
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__raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
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XEL_RSR_RECV_IE_MASK);
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/* Enable the Rx interrupts for the second Buffer if
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/* Enable the Rx interrupts for the second Buffer if
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* configured in HW */
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* configured in HW */
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if (drvdata->rx_ping_pong != 0) {
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if (drvdata->rx_ping_pong != 0) {
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out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
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__raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr +
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XEL_RSR_OFFSET,
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XEL_BUFFER_OFFSET + XEL_RSR_OFFSET);
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XEL_RSR_RECV_IE_MASK);
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}
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}
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/* Enable the Global Interrupt Enable */
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/* Enable the Global Interrupt Enable */
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out_be32(drvdata->base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
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__raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
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}
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}
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/**
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/**
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@ -201,37 +199,37 @@ static void xemaclite_disable_interrupts(struct net_local *drvdata)
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u32 reg_data;
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u32 reg_data;
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/* Disable the Global Interrupt Enable */
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/* Disable the Global Interrupt Enable */
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out_be32(drvdata->base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
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__raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
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/* Disable the Tx interrupts for the first buffer */
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/* Disable the Tx interrupts for the first buffer */
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reg_data = in_be32(drvdata->base_addr + XEL_TSR_OFFSET);
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reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
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out_be32(drvdata->base_addr + XEL_TSR_OFFSET,
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__raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
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reg_data & (~XEL_TSR_XMIT_IE_MASK));
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drvdata->base_addr + XEL_TSR_OFFSET);
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/* Disable the Tx interrupts for the second Buffer
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/* Disable the Tx interrupts for the second Buffer
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* if configured in HW */
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* if configured in HW */
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if (drvdata->tx_ping_pong != 0) {
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if (drvdata->tx_ping_pong != 0) {
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reg_data = in_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
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reg_data = __raw_readl(drvdata->base_addr + XEL_BUFFER_OFFSET +
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XEL_TSR_OFFSET);
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__raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
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drvdata->base_addr + XEL_BUFFER_OFFSET +
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XEL_TSR_OFFSET);
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XEL_TSR_OFFSET);
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out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
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XEL_TSR_OFFSET,
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reg_data & (~XEL_TSR_XMIT_IE_MASK));
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}
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}
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/* Disable the Rx interrupts for the first buffer */
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/* Disable the Rx interrupts for the first buffer */
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reg_data = in_be32(drvdata->base_addr + XEL_RSR_OFFSET);
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reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET);
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out_be32(drvdata->base_addr + XEL_RSR_OFFSET,
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__raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
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reg_data & (~XEL_RSR_RECV_IE_MASK));
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drvdata->base_addr + XEL_RSR_OFFSET);
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/* Disable the Rx interrupts for the second buffer
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/* Disable the Rx interrupts for the second buffer
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* if configured in HW */
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* if configured in HW */
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if (drvdata->rx_ping_pong != 0) {
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if (drvdata->rx_ping_pong != 0) {
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reg_data = in_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
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reg_data = __raw_readl(drvdata->base_addr + XEL_BUFFER_OFFSET +
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XEL_RSR_OFFSET);
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__raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
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drvdata->base_addr + XEL_BUFFER_OFFSET +
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XEL_RSR_OFFSET);
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XEL_RSR_OFFSET);
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out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
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XEL_RSR_OFFSET,
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reg_data & (~XEL_RSR_RECV_IE_MASK));
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}
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}
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}
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}
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@ -351,7 +349,7 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
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byte_count = ETH_FRAME_LEN;
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byte_count = ETH_FRAME_LEN;
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/* Check if the expected buffer is available */
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/* Check if the expected buffer is available */
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reg_data = in_be32(addr + XEL_TSR_OFFSET);
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reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
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if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
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XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
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XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
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@ -364,7 +362,7 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
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addr = (void __iomem __force *)((u32 __force)addr ^
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addr = (void __iomem __force *)((u32 __force)addr ^
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XEL_BUFFER_OFFSET);
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XEL_BUFFER_OFFSET);
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reg_data = in_be32(addr + XEL_TSR_OFFSET);
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reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
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if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
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XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
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XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
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@ -375,15 +373,16 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
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/* Write the frame to the buffer */
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/* Write the frame to the buffer */
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xemaclite_aligned_write(data, (u32 __force *) addr, byte_count);
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xemaclite_aligned_write(data, (u32 __force *) addr, byte_count);
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out_be32(addr + XEL_TPLR_OFFSET, (byte_count & XEL_TPLR_LENGTH_MASK));
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__raw_writel((byte_count & XEL_TPLR_LENGTH_MASK),
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addr + XEL_TPLR_OFFSET);
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/* Update the Tx Status Register to indicate that there is a
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/* Update the Tx Status Register to indicate that there is a
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* frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
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* frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
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* is used by the interrupt handler to check whether a frame
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* is used by the interrupt handler to check whether a frame
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* has been transmitted */
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* has been transmitted */
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reg_data = in_be32(addr + XEL_TSR_OFFSET);
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reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
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reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
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out_be32(addr + XEL_TSR_OFFSET, reg_data);
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__raw_writel(reg_data, addr + XEL_TSR_OFFSET);
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return 0;
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return 0;
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}
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}
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@ -408,7 +407,7 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
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addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
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/* Verify which buffer has valid data */
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/* Verify which buffer has valid data */
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reg_data = in_be32(addr + XEL_RSR_OFFSET);
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reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
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if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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if (drvdata->rx_ping_pong != 0)
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if (drvdata->rx_ping_pong != 0)
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@ -425,14 +424,14 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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return 0; /* No data was available */
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return 0; /* No data was available */
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/* Verify that buffer has valid data */
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/* Verify that buffer has valid data */
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reg_data = in_be32(addr + XEL_RSR_OFFSET);
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reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
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if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
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if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
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XEL_RSR_RECV_DONE_MASK)
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XEL_RSR_RECV_DONE_MASK)
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return 0; /* No data was available */
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return 0; /* No data was available */
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}
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}
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/* Get the protocol type of the ethernet frame that arrived */
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/* Get the protocol type of the ethernet frame that arrived */
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proto_type = ((ntohl(in_be32(addr + XEL_HEADER_OFFSET +
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proto_type = ((ntohl(__raw_readl(addr + XEL_HEADER_OFFSET +
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XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
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XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
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XEL_RPLR_LENGTH_MASK);
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XEL_RPLR_LENGTH_MASK);
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@ -441,7 +440,7 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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if (proto_type > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
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if (proto_type > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
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if (proto_type == ETH_P_IP) {
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if (proto_type == ETH_P_IP) {
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length = ((ntohl(in_be32(addr +
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length = ((ntohl(__raw_readl(addr +
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XEL_HEADER_IP_LENGTH_OFFSET +
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XEL_HEADER_IP_LENGTH_OFFSET +
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XEL_RXBUFF_OFFSET)) >>
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XEL_RXBUFF_OFFSET)) >>
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XEL_HEADER_SHIFT) &
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XEL_HEADER_SHIFT) &
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@ -463,9 +462,9 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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data, length);
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data, length);
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/* Acknowledge the frame */
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/* Acknowledge the frame */
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reg_data = in_be32(addr + XEL_RSR_OFFSET);
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reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
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reg_data &= ~XEL_RSR_RECV_DONE_MASK;
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reg_data &= ~XEL_RSR_RECV_DONE_MASK;
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out_be32(addr + XEL_RSR_OFFSET, reg_data);
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__raw_writel(reg_data, addr + XEL_RSR_OFFSET);
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return length;
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return length;
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}
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}
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@ -492,14 +491,14 @@ static void xemaclite_update_address(struct net_local *drvdata,
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xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN);
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xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN);
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out_be32(addr + XEL_TPLR_OFFSET, ETH_ALEN);
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__raw_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
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/* Update the MAC address in the EmacLite */
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/* Update the MAC address in the EmacLite */
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reg_data = in_be32(addr + XEL_TSR_OFFSET);
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reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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out_be32(addr + XEL_TSR_OFFSET, reg_data | XEL_TSR_PROG_MAC_ADDR);
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__raw_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
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/* Wait for EmacLite to finish with the MAC address update */
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/* Wait for EmacLite to finish with the MAC address update */
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while ((in_be32(addr + XEL_TSR_OFFSET) &
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while ((__raw_readl(addr + XEL_TSR_OFFSET) &
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XEL_TSR_PROG_MAC_ADDR) != 0)
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XEL_TSR_PROG_MAC_ADDR) != 0)
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;
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;
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}
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}
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@ -669,31 +668,32 @@ static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
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u32 tx_status;
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u32 tx_status;
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/* Check if there is Rx Data available */
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/* Check if there is Rx Data available */
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if ((in_be32(base_addr + XEL_RSR_OFFSET) & XEL_RSR_RECV_DONE_MASK) ||
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if ((__raw_readl(base_addr + XEL_RSR_OFFSET) &
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(in_be32(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
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XEL_RSR_RECV_DONE_MASK) ||
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(__raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
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& XEL_RSR_RECV_DONE_MASK))
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& XEL_RSR_RECV_DONE_MASK))
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xemaclite_rx_handler(dev);
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xemaclite_rx_handler(dev);
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/* Check if the Transmission for the first buffer is completed */
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/* Check if the Transmission for the first buffer is completed */
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tx_status = in_be32(base_addr + XEL_TSR_OFFSET);
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tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET);
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if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
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if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
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(tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
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(tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
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tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
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tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
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out_be32(base_addr + XEL_TSR_OFFSET, tx_status);
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__raw_writel(tx_status, base_addr + XEL_TSR_OFFSET);
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tx_complete = true;
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tx_complete = true;
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}
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}
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/* Check if the Transmission for the second buffer is completed */
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/* Check if the Transmission for the second buffer is completed */
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tx_status = in_be32(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
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if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
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(tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
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(tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
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tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
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tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
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out_be32(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET,
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__raw_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
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tx_status);
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XEL_TSR_OFFSET);
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tx_complete = true;
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tx_complete = true;
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}
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}
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@ -726,7 +726,7 @@ static int xemaclite_mdio_wait(struct net_local *lp)
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/* wait for the MDIO interface to not be busy or timeout
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/* wait for the MDIO interface to not be busy or timeout
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after some time.
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after some time.
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*/
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*/
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while (in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET) &
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while (__raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) &
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XEL_MDIOCTRL_MDIOSTS_MASK) {
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XEL_MDIOCTRL_MDIOSTS_MASK) {
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if (end - jiffies <= 0) {
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if (end - jiffies <= 0) {
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WARN_ON(1);
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WARN_ON(1);
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@ -762,17 +762,17 @@ static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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* MDIO Address register. Set the Status bit in the MDIO Control
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* MDIO Address register. Set the Status bit in the MDIO Control
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* register to start a MDIO read transaction.
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* register to start a MDIO read transaction.
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*/
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*/
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ctrl_reg = in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET);
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ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
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out_be32(lp->base_addr + XEL_MDIOADDR_OFFSET,
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__raw_writel(XEL_MDIOADDR_OP_MASK |
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XEL_MDIOADDR_OP_MASK |
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((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
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((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg));
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lp->base_addr + XEL_MDIOADDR_OFFSET);
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out_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET,
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__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
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ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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lp->base_addr + XEL_MDIOCTRL_OFFSET);
|
||||||
|
|
||||||
if (xemaclite_mdio_wait(lp))
|
if (xemaclite_mdio_wait(lp))
|
||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
rc = in_be32(lp->base_addr + XEL_MDIORD_OFFSET);
|
rc = __raw_readl(lp->base_addr + XEL_MDIORD_OFFSET);
|
||||||
|
|
||||||
dev_dbg(&lp->ndev->dev,
|
dev_dbg(&lp->ndev->dev,
|
||||||
"xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",
|
"xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",
|
||||||
@ -809,13 +809,13 @@ static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
|
|||||||
* Data register. Finally, set the Status bit in the MDIO Control
|
* Data register. Finally, set the Status bit in the MDIO Control
|
||||||
* register to start a MDIO write transaction.
|
* register to start a MDIO write transaction.
|
||||||
*/
|
*/
|
||||||
ctrl_reg = in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET);
|
ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
|
||||||
out_be32(lp->base_addr + XEL_MDIOADDR_OFFSET,
|
__raw_writel(~XEL_MDIOADDR_OP_MASK &
|
||||||
~XEL_MDIOADDR_OP_MASK &
|
((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
|
||||||
((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg));
|
lp->base_addr + XEL_MDIOADDR_OFFSET);
|
||||||
out_be32(lp->base_addr + XEL_MDIOWR_OFFSET, val);
|
__raw_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
|
||||||
out_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET,
|
__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
|
||||||
ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
|
lp->base_addr + XEL_MDIOCTRL_OFFSET);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -872,8 +872,8 @@ static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
|
|||||||
/* Enable the MDIO bus by asserting the enable bit in MDIO Control
|
/* Enable the MDIO bus by asserting the enable bit in MDIO Control
|
||||||
* register.
|
* register.
|
||||||
*/
|
*/
|
||||||
out_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET,
|
__raw_writel(XEL_MDIOCTRL_MDIOEN_MASK,
|
||||||
XEL_MDIOCTRL_MDIOEN_MASK);
|
lp->base_addr + XEL_MDIOCTRL_OFFSET);
|
||||||
|
|
||||||
bus = mdiobus_alloc();
|
bus = mdiobus_alloc();
|
||||||
if (!bus) {
|
if (!bus) {
|
||||||
@ -1197,8 +1197,8 @@ static int xemaclite_of_probe(struct platform_device *ofdev)
|
|||||||
dev_warn(dev, "No MAC address found\n");
|
dev_warn(dev, "No MAC address found\n");
|
||||||
|
|
||||||
/* Clear the Tx CSR's in case this is a restart */
|
/* Clear the Tx CSR's in case this is a restart */
|
||||||
out_be32(lp->base_addr + XEL_TSR_OFFSET, 0);
|
__raw_writel(0, lp->base_addr + XEL_TSR_OFFSET);
|
||||||
out_be32(lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET, 0);
|
__raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
|
||||||
|
|
||||||
/* Set the MAC address in the EmacLite device */
|
/* Set the MAC address in the EmacLite device */
|
||||||
xemaclite_update_address(lp, ndev->dev_addr);
|
xemaclite_update_address(lp, ndev->dev_addr);
|
||||||
|
Loading…
Reference in New Issue
Block a user