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drm/i915: Make valleyview_display_irqs_(un)install() work for chv
Genralize valleyview_display_irqs_install() and valleyview_display_irqs_uninstall() enough so that they work on chv. The only difference to vlv here being the third pipe that chv brings. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3335,24 +3335,27 @@ static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
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{
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u32 pipestat_mask;
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u32 iir_mask;
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enum pipe pipe;
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pipestat_mask = PIPESTAT_INT_STATUS_MASK |
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PIPE_FIFO_UNDERRUN_STATUS;
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I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
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I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
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for_each_pipe(dev_priv, pipe)
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I915_WRITE(PIPESTAT(pipe), pipestat_mask);
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POSTING_READ(PIPESTAT(PIPE_A));
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pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
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PIPE_CRC_DONE_INTERRUPT_STATUS;
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i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
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PIPE_GMBUS_INTERRUPT_STATUS);
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i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
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i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
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for_each_pipe(dev_priv, pipe)
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i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
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iir_mask = I915_DISPLAY_PORT_INTERRUPT |
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
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if (IS_CHERRYVIEW(dev_priv))
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iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
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dev_priv->irq_mask &= ~iir_mask;
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I915_WRITE(VLV_IIR, iir_mask);
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@ -3366,10 +3369,13 @@ static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
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{
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u32 pipestat_mask;
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u32 iir_mask;
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enum pipe pipe;
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iir_mask = I915_DISPLAY_PORT_INTERRUPT |
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
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if (IS_CHERRYVIEW(dev_priv))
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iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
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dev_priv->irq_mask |= iir_mask;
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I915_WRITE(VLV_IMR, dev_priv->irq_mask);
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@ -3381,14 +3387,15 @@ static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
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pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
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PIPE_CRC_DONE_INTERRUPT_STATUS;
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i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
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PIPE_GMBUS_INTERRUPT_STATUS);
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i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
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i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
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for_each_pipe(dev_priv, pipe)
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i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
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pipestat_mask = PIPESTAT_INT_STATUS_MASK |
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PIPE_FIFO_UNDERRUN_STATUS;
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I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
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I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
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for_each_pipe(dev_priv, pipe)
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I915_WRITE(PIPESTAT(pipe), pipestat_mask);
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POSTING_READ(PIPESTAT(PIPE_A));
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}
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