mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Blackfin: unify pll.h headers
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
73a400646b
commit
10cdc1a78a
86
arch/blackfin/include/mach-common/pll.h
Normal file
86
arch/blackfin/include/mach-common/pll.h
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@ -0,0 +1,86 @@
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/*
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* Copyright 2005-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_COMMON_PLL_H
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#define _MACH_COMMON_PLL_H
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#ifndef __ASSEMBLY__
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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#ifndef bfin_iwr_restore
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static inline void
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bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
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{
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#ifdef SIC_IWR
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bfin_write_SIC_IWR(iwr0);
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#else
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bfin_write_SIC_IWR0(iwr0);
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# ifdef SIC_IWR1
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bfin_write_SIC_IWR1(iwr1);
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# endif
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(iwr2);
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# endif
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#endif
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}
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#endif
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#ifndef bfin_iwr_save
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static inline void
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bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
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unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
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{
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#ifdef SIC_IWR
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*iwr0 = bfin_read_SIC_IWR();
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#else
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*iwr0 = bfin_read_SIC_IWR0();
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# ifdef SIC_IWR1
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*iwr1 = bfin_read_SIC_IWR1();
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# endif
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# ifdef SIC_IWR2
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*iwr2 = bfin_read_SIC_IWR2();
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# endif
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#endif
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bfin_iwr_restore(niwr0, niwr1, niwr2);
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}
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#endif
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static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
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{
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unsigned long flags, iwr0, iwr1, iwr2;
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if (val == bfin_read_PLL_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
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bfin_write16(addr, val);
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SSYNC();
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asm("IDLE;");
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bfin_iwr_restore(iwr0, iwr1, iwr2);
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hard_local_irq_restore(flags);
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}
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/* Writing to PLL_CTL initiates a PLL relock sequence */
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static inline void bfin_write_PLL_CTL(unsigned int val)
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{
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_bfin_write_pll_relock(PLL_CTL, val);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence */
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static inline void bfin_write_VR_CTL(unsigned int val)
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{
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_bfin_write_pll_relock(VR_CTL, val);
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}
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#endif
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#endif
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@ -1,63 +1 @@
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/*
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#include <mach-common/pll.h>
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* Copyright 2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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hard_local_irq_restore(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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hard_local_irq_restore(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -1,63 +1 @@
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/*
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#include <mach-common/pll.h>
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* Copyright 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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hard_local_irq_restore(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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hard_local_irq_restore(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -1,57 +1 @@
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/*
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#include <mach-common/pll.h>
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* Copyright 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_PLL_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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hard_local_irq_restore(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_VR_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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hard_local_irq_restore(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -1,57 +1 @@
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/*
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#include <mach-common/pll.h>
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* Copyright 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_PLL_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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hard_local_irq_restore(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_VR_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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hard_local_irq_restore(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -1,63 +1 @@
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/*
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#include <mach-common/pll.h>
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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hard_local_irq_restore(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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flags = hard_local_irq_save();
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
|
|
||||||
|
|
||||||
bfin_write32(SIC_IWR0, iwr0);
|
|
||||||
bfin_write32(SIC_IWR1, iwr1);
|
|
||||||
hard_local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* _MACH_PLL_H */
|
|
||||||
|
|||||||
@ -1,69 +1 @@
|
|||||||
/*
|
#include <mach-common/pll.h>
|
||||||
* Copyright 2007-2008 Analog Devices Inc.
|
|
||||||
*
|
|
||||||
* Licensed under the GPL-2 or later.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _MACH_PLL_H
|
|
||||||
#define _MACH_PLL_H
|
|
||||||
|
|
||||||
#include <asm/blackfin.h>
|
|
||||||
#include <asm/irqflags.h>
|
|
||||||
|
|
||||||
/* Writing to PLL_CTL initiates a PLL relock sequence. */
|
|
||||||
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
|
|
||||||
{
|
|
||||||
unsigned long flags, iwr0, iwr1, iwr2;
|
|
||||||
|
|
||||||
if (val == bfin_read_PLL_CTL())
|
|
||||||
return;
|
|
||||||
|
|
||||||
flags = hard_local_irq_save();
|
|
||||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
|
||||||
iwr0 = bfin_read32(SIC_IWR0);
|
|
||||||
iwr1 = bfin_read32(SIC_IWR1);
|
|
||||||
iwr2 = bfin_read32(SIC_IWR2);
|
|
||||||
/* Only allow PPL Wakeup) */
|
|
||||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
|
||||||
bfin_write32(SIC_IWR1, 0);
|
|
||||||
bfin_write32(SIC_IWR2, 0);
|
|
||||||
|
|
||||||
bfin_write16(PLL_CTL, val);
|
|
||||||
SSYNC();
|
|
||||||
asm("IDLE;");
|
|
||||||
|
|
||||||
bfin_write32(SIC_IWR0, iwr0);
|
|
||||||
bfin_write32(SIC_IWR1, iwr1);
|
|
||||||
bfin_write32(SIC_IWR2, iwr2);
|
|
||||||
hard_local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
|
||||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
|
||||||
{
|
|
||||||
unsigned long flags, iwr0, iwr1, iwr2;
|
|
||||||
|
|
||||||
if (val == bfin_read_VR_CTL())
|
|
||||||
return;
|
|
||||||
|
|
||||||
flags = hard_local_irq_save();
|
|
||||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
|
||||||
iwr0 = bfin_read32(SIC_IWR0);
|
|
||||||
iwr1 = bfin_read32(SIC_IWR1);
|
|
||||||
iwr2 = bfin_read32(SIC_IWR2);
|
|
||||||
/* Only allow PPL Wakeup) */
|
|
||||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
|
||||||
bfin_write32(SIC_IWR1, 0);
|
|
||||||
bfin_write32(SIC_IWR2, 0);
|
|
||||||
|
|
||||||
bfin_write16(VR_CTL, val);
|
|
||||||
SSYNC();
|
|
||||||
asm("IDLE;");
|
|
||||||
|
|
||||||
bfin_write32(SIC_IWR0, iwr0);
|
|
||||||
bfin_write32(SIC_IWR1, iwr1);
|
|
||||||
bfin_write32(SIC_IWR2, iwr2);
|
|
||||||
hard_local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* _MACH_PLL_H */
|
|
||||||
|
|||||||
@ -1,63 +1 @@
|
|||||||
/*
|
#include <mach-common/pll.h>
|
||||||
* Copyright 2005-2009 Analog Devices Inc.
|
|
||||||
*
|
|
||||||
* Licensed under the GPL-2 or later.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _MACH_PLL_H
|
|
||||||
#define _MACH_PLL_H
|
|
||||||
|
|
||||||
#include <asm/blackfin.h>
|
|
||||||
#include <asm/irqflags.h>
|
|
||||||
|
|
||||||
/* Writing to PLL_CTL initiates a PLL relock sequence. */
|
|
||||||
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
|
|
||||||
{
|
|
||||||
unsigned long flags, iwr0, iwr1;
|
|
||||||
|
|
||||||
if (val == bfin_read_PLL_CTL())
|
|
||||||
return;
|
|
||||||
|
|
||||||
flags = hard_local_irq_save();
|
|
||||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
|
||||||
iwr0 = bfin_read32(SIC_IWR0);
|
|
||||||
iwr1 = bfin_read32(SIC_IWR1);
|
|
||||||
/* Only allow PPL Wakeup) */
|
|
||||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
|
||||||
bfin_write32(SIC_IWR1, 0);
|
|
||||||
|
|
||||||
bfin_write16(PLL_CTL, val);
|
|
||||||
SSYNC();
|
|
||||||
asm("IDLE;");
|
|
||||||
|
|
||||||
bfin_write32(SIC_IWR0, iwr0);
|
|
||||||
bfin_write32(SIC_IWR1, iwr1);
|
|
||||||
hard_local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
|
||||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
|
||||||
{
|
|
||||||
unsigned long flags, iwr0, iwr1;
|
|
||||||
|
|
||||||
if (val == bfin_read_VR_CTL())
|
|
||||||
return;
|
|
||||||
|
|
||||||
flags = hard_local_irq_save();
|
|
||||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
|
||||||
iwr0 = bfin_read32(SIC_IWR0);
|
|
||||||
iwr1 = bfin_read32(SIC_IWR1);
|
|
||||||
/* Only allow PPL Wakeup) */
|
|
||||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
|
||||||
bfin_write32(SIC_IWR1, 0);
|
|
||||||
|
|
||||||
bfin_write16(VR_CTL, val);
|
|
||||||
SSYNC();
|
|
||||||
asm("IDLE;");
|
|
||||||
|
|
||||||
bfin_write32(SIC_IWR0, iwr0);
|
|
||||||
bfin_write32(SIC_IWR1, iwr1);
|
|
||||||
hard_local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* _MACH_PLL_H */
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user