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drm/amd/display: program DPG_OFFSET_SEGMENT for odm_pipe

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[why]
When test pattern is enabled with ODM combine, test pattern is generated
by piecing multiple DPGs image together.  The current code will program
all DPGs with horizontal offset of 0. This will cause all DPGs to output
the beginning of the pattern. Instead each DPG should program a
horizontal offset of its x position to form a continous pattern when
pieced together.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wenjing Liu 2020-02-11 10:27:21 -05:00 committed by Alex Deucher
parent e8f9ecf261
commit 10b4e64e58
5 changed files with 49 additions and 23 deletions
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40
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -3720,6 +3720,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
struct pipe_ctx *odm_pipe; struct pipe_ctx *odm_pipe;
enum controller_dp_color_space controller_color_space; enum controller_dp_color_space controller_color_space;
int opp_cnt = 1; int opp_cnt = 1;
int offset = 0;
int dpg_width = width;
switch (test_pattern_color_space) { switch (test_pattern_color_space) {
case DP_TEST_PATTERN_COLOR_SPACE_RGB: case DP_TEST_PATTERN_COLOR_SPACE_RGB:
@ -3741,28 +3743,31 @@ static void set_crtc_test_pattern(struct dc_link *link,
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
opp_cnt++; opp_cnt++;
dpg_width = width / opp_cnt;
offset = dpg_width;
width /= opp_cnt; opp->funcs->opp_set_disp_pattern_generator(opp,
controller_test_pattern,
controller_color_space,
color_depth,
NULL,
dpg_width,
height,
0);
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params); odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp, odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
controller_test_pattern, controller_test_pattern,
controller_color_space, controller_color_space,
color_depth, color_depth,
NULL, NULL,
width, dpg_width,
height); height,
offset);
offset += offset;
} }
opp->funcs->opp_set_disp_pattern_generator(opp,
controller_test_pattern,
controller_color_space,
color_depth,
NULL,
width,
height);
} }
} }
break; break;
@ -3779,11 +3784,12 @@ static void set_crtc_test_pattern(struct dc_link *link,
else if (opp->funcs->opp_set_disp_pattern_generator) { else if (opp->funcs->opp_set_disp_pattern_generator) {
struct pipe_ctx *odm_pipe; struct pipe_ctx *odm_pipe;
int opp_cnt = 1; int opp_cnt = 1;
int dpg_width = width;
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
opp_cnt++; opp_cnt++;
width /= opp_cnt; dpg_width = width / opp_cnt;
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
@ -3793,16 +3799,18 @@ static void set_crtc_test_pattern(struct dc_link *link,
CONTROLLER_DP_COLOR_SPACE_UDEFINED, CONTROLLER_DP_COLOR_SPACE_UDEFINED,
color_depth, color_depth,
NULL, NULL,
width, dpg_width,
height); height,
0);
} }
opp->funcs->opp_set_disp_pattern_generator(opp, opp->funcs->opp_set_disp_pattern_generator(opp,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
CONTROLLER_DP_COLOR_SPACE_UDEFINED, CONTROLLER_DP_COLOR_SPACE_UDEFINED,
color_depth, color_depth,
NULL, NULL,
width, dpg_width,
height); height,
0);
} }
} }
break; break;

12
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -307,7 +307,8 @@ void dcn20_init_blank(
COLOR_DEPTH_UNDEFINED, COLOR_DEPTH_UNDEFINED,
&black_color, &black_color,
otg_active_width, otg_active_width,
otg_active_height); otg_active_height,
0);
if (num_opps == 2) { if (num_opps == 2) {
bottom_opp->funcs->opp_set_disp_pattern_generator( bottom_opp->funcs->opp_set_disp_pattern_generator(
@ -317,7 +318,8 @@ void dcn20_init_blank(
COLOR_DEPTH_UNDEFINED, COLOR_DEPTH_UNDEFINED,
&black_color, &black_color,
otg_active_width, otg_active_width,
otg_active_height); otg_active_height,
0);
} }
hws->funcs.wait_for_blank_complete(opp); hws->funcs.wait_for_blank_complete(opp);
@ -974,7 +976,8 @@ void dcn20_blank_pixel_data(
stream->timing.display_color_depth, stream->timing.display_color_depth,
&black_color, &black_color,
width, width,
height); height,
0);
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
@ -985,7 +988,8 @@ void dcn20_blank_pixel_data(
stream->timing.display_color_depth, stream->timing.display_color_depth,
&black_color, &black_color,
width, width,
height); height,
0);
} }
if (!blank) if (!blank)

8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
View File

@ -45,7 +45,8 @@ void opp2_set_disp_pattern_generator(
enum dc_color_depth color_depth, enum dc_color_depth color_depth,
const struct tg_color *solid_color, const struct tg_color *solid_color,
int width, int width,
int height) int height,
int offset)
{ {
struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
enum test_pattern_color_format bit_depth; enum test_pattern_color_format bit_depth;
@ -92,6 +93,11 @@ void opp2_set_disp_pattern_generator(
DPG_ACTIVE_WIDTH, width, DPG_ACTIVE_WIDTH, width,
DPG_ACTIVE_HEIGHT, height); DPG_ACTIVE_HEIGHT, height);
/* set DPG offset */
REG_SET_2(DPG_OFFSET_SEGMENT, 0,
DPG_X_OFFSET, offset,
DPG_SEGMENT_WIDTH, 0);
switch (test_pattern) { switch (test_pattern) {
case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:

9
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
View File

@ -36,6 +36,7 @@
#define OPP_DPG_REG_LIST(id) \ #define OPP_DPG_REG_LIST(id) \
SRI(DPG_CONTROL, DPG, id), \ SRI(DPG_CONTROL, DPG, id), \
SRI(DPG_DIMENSIONS, DPG, id), \ SRI(DPG_DIMENSIONS, DPG, id), \
SRI(DPG_OFFSET_SEGMENT, DPG, id), \
SRI(DPG_COLOUR_B_CB, DPG, id), \ SRI(DPG_COLOUR_B_CB, DPG, id), \
SRI(DPG_COLOUR_G_Y, DPG, id), \ SRI(DPG_COLOUR_G_Y, DPG, id), \
SRI(DPG_COLOUR_R_CR, DPG, id), \ SRI(DPG_COLOUR_R_CR, DPG, id), \
@ -53,6 +54,7 @@
uint32_t FMT_422_CONTROL; \ uint32_t FMT_422_CONTROL; \
uint32_t DPG_CONTROL; \ uint32_t DPG_CONTROL; \
uint32_t DPG_DIMENSIONS; \ uint32_t DPG_DIMENSIONS; \
uint32_t DPG_OFFSET_SEGMENT; \
uint32_t DPG_COLOUR_B_CB; \ uint32_t DPG_COLOUR_B_CB; \
uint32_t DPG_COLOUR_G_Y; \ uint32_t DPG_COLOUR_G_Y; \
uint32_t DPG_COLOUR_R_CR; \ uint32_t DPG_COLOUR_R_CR; \
@ -68,6 +70,8 @@
OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \ OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \
OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \ OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \
OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \ OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \
OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_X_OFFSET, mask_sh), \
OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_SEGMENT_WIDTH, mask_sh), \
OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \ OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \
OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \ OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \
OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \ OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \
@ -97,6 +101,8 @@
type DPG_HRES; \ type DPG_HRES; \
type DPG_ACTIVE_WIDTH; \ type DPG_ACTIVE_WIDTH; \
type DPG_ACTIVE_HEIGHT; \ type DPG_ACTIVE_HEIGHT; \
type DPG_X_OFFSET; \
type DPG_SEGMENT_WIDTH; \
type DPG_COLOUR0_R_CR; \ type DPG_COLOUR0_R_CR; \
type DPG_COLOUR1_R_CR; \ type DPG_COLOUR1_R_CR; \
type DPG_COLOUR0_B_CB; \ type DPG_COLOUR0_B_CB; \
@ -144,7 +150,8 @@ void opp2_set_disp_pattern_generator(
enum dc_color_depth color_depth, enum dc_color_depth color_depth,
const struct tg_color *solid_color, const struct tg_color *solid_color,
int width, int width,
int height); int height,
int offset);
bool opp2_dpg_is_blanked(struct output_pixel_processor *opp); bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);

3
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
View File

@ -310,7 +310,8 @@ struct opp_funcs {
enum dc_color_depth color_depth, enum dc_color_depth color_depth,
const struct tg_color *solid_color, const struct tg_color *solid_color,
int width, int width,
int height); int height,
int offset);
bool (*dpg_is_blanked)( bool (*dpg_is_blanked)(
struct output_pixel_processor *opp); struct output_pixel_processor *opp);