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x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features

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Both AMD and Intel can have SPEC_CTRL_MSR for SSBD.

However AMD also has two more other ways of doing it - which
are !SPEC_CTRL MSR ways.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Kees Cook <keescook@chromium.org>
Cc: kvm@vger.kernel.org
Cc: KarimAllah Ahmed <karahmed@amazon.de>
Cc: andrew.cooper3@citrix.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Link: https://lkml.kernel.org/r/20180601145921.9500-4-konrad.wilk@oracle.com
This commit is contained in:
Konrad Rzeszutek Wilk 2018-06-01 10:59:21 -04:00 committed by Thomas Gleixner
parent 6ac2f49edb
commit 108fab4b5c
1 changed files with 3 additions and 8 deletions
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9
arch/x86/kernel/cpu/bugs.c
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@ -532,17 +532,12 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
* use a completely different MSR and bit dependent on family. * use a completely different MSR and bit dependent on family.
*/ */
switch (boot_cpu_data.x86_vendor) { if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
case X86_VENDOR_INTEL:
case X86_VENDOR_AMD:
if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
x86_amd_ssb_disable(); x86_amd_ssb_disable();
break; else {
}
x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
break;
} }
} }