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ARM: dts: add dts files for exynos5410 and exynos5410-smdk5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board. Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tarek Dakhran
Kukjin Kim
parent
5a992a9c98
commit
107e6aad98
@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
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exynos5250-smdk5250.dtb \
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exynos5250-snow.dtb \
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exynos5260-xyref5260.dtb \
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exynos5410-smdk5410.dtb \
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exynos5420-arndale-octa.dtb \
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exynos5420-peach-pit.dtb \
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exynos5420-smdk5420.dtb \
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82
arch/arm/boot/dts/exynos5410-smdk5410.dts
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82
arch/arm/boot/dts/exynos5410-smdk5410.dts
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@ -0,0 +1,82 @@
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/*
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* SAMSUNG SMDK5410 board device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "exynos5410.dtsi"
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/ {
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model = "Samsung SMDK5410 board based on EXYNOS5410";
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compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
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memory {
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reg = <0x40000000 0x80000000>;
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};
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chosen {
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bootargs = "console=ttySAC2,115200";
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};
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fin_pll: xxti {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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};
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firmware@02037000 {
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compatible = "samsung,secure-firmware";
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reg = <0x02037000 0x1000>;
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};
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};
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&mmc_0 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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card-detect-delay = <200>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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slot@0 {
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reg = <0>;
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bus-width = <8>;
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};
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};
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&mmc_2 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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card-detect-delay = <200>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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disable-wp;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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206
arch/arm/boot/dts/exynos5410.dtsi
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206
arch/arm/boot/dts/exynos5410.dtsi
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@ -0,0 +1,206 @@
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/*
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* SAMSUNG EXYNOS5410 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
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* EXYNOS5410 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/exynos5410.h>
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/ {
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compatible = "samsung,exynos5410", "samsung,exynos5";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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combiner: interrupt-controller@10440000 {
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compatible = "samsung,exynos4210-combiner";
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#interrupt-cells = <2>;
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interrupt-controller;
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samsung,combiner-nr = <32>;
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reg = <0x10440000 0x1000>;
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interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
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<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
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<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
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<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
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<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
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<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
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<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
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<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
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};
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gic: interrupt-controller@10481000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10481000 0x1000>,
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<0x10482000 0x1000>,
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<0x10484000 0x2000>,
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<0x10486000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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mct: mct@101C0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0xB00>;
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interrupt-parent = <&interrupt_map>;
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interrupts = <0>, <1>, <2>, <3>,
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<4>, <5>, <6>, <7>,
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<8>, <9>, <10>, <11>;
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clocks = <&fin_pll>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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interrupt_map: interrupt-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &combiner 23 3>,
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<1 &combiner 23 4>,
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<2 &combiner 25 2>,
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<3 &combiner 25 3>,
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<4 &gic 0 120 0>,
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<5 &gic 0 121 0>,
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<6 &gic 0 122 0>,
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<7 &gic 0 123 0>,
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<8 &gic 0 128 0>,
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<9 &gic 0 129 0>,
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<10 &gic 0 130 0>,
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<11 &gic 0 131 0>;
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};
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x54000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x54000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@53000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x53000 0x1000>;
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};
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5410-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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mmc_0: mmc@12200000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12200000 0x1000>;
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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status = "disabled";
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};
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mmc_1: mmc@12210000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12210000 0x1000>;
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interrupts = <0 76 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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status = "disabled";
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};
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mmc_2: mmc@12220000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12220000 0x1000>;
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interrupts = <0 77 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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status = "disabled";
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};
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uart0: serial@12C00000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <0 51 0>;
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clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart1: serial@12C10000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C10000 0x100>;
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interrupts = <0 52 0>;
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clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart2: serial@12C20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C20000 0x100>;
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interrupts = <0 53 0>;
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clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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};
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};
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