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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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EDAC, ghes: Model a single, logical memory controller
We're enumerating the DIMMs through a DMI walk and since we can't get any more detailed topological information about which DIMMs belong to which memory controller, convert it to a single, logical controller which contains all the DIMMs. The error reporting path from GHES ghes_edac_report_mem_error() doesn't get called in NMI context but add a warning about it to catch any changes in the future as if so, our locking scheme will be insufficient then. Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Borislav Petkov
parent
c9c8b4d6d0
commit
0fe5f281f7
@ -28,10 +28,15 @@ struct ghes_edac_pvt {
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char msg[80];
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};
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static LIST_HEAD(ghes_reglist);
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static DEFINE_MUTEX(ghes_edac_lock);
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static int ghes_edac_mc_num;
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static atomic_t ghes_init = ATOMIC_INIT(0);
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static struct ghes_edac_pvt *ghes_pvt;
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/*
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* Sync with other, potentially concurrent callers of
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* ghes_edac_report_mem_error(). We don't know what the
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* "inventive" firmware would do.
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*/
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static DEFINE_SPINLOCK(ghes_lock);
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/* Memory Device - Type 17 of SMBIOS spec */
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struct memdev_dmi_entry {
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@ -169,18 +174,26 @@ void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
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enum hw_event_mc_err_type type;
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struct edac_raw_error_desc *e;
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struct mem_ctl_info *mci;
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struct ghes_edac_pvt *pvt = NULL;
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struct ghes_edac_pvt *pvt = ghes_pvt;
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unsigned long flags;
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char *p;
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u8 grain_bits;
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list_for_each_entry(pvt, &ghes_reglist, list) {
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if (ghes == pvt->ghes)
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break;
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}
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if (!pvt) {
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pr_err("Internal error: Can't find EDAC structure\n");
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return;
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}
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/*
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* We can do the locking below because GHES defers error processing
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* from NMI to IRQ context. Whenever that changes, we'd at least
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* know.
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*/
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if (WARN_ON_ONCE(in_nmi()))
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return;
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spin_lock_irqsave(&ghes_lock, flags);
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mci = pvt->mci;
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e = &mci->error_desc;
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@ -398,8 +411,8 @@ void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
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(e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
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grain_bits, e->syndrome, pvt->detail_location);
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/* Report the error via EDAC API */
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edac_raw_mc_handle_error(type, mci, e);
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spin_unlock_irqrestore(&ghes_lock, flags);
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}
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int ghes_edac_register(struct ghes *ghes, struct device *dev)
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@ -408,9 +421,14 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
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int rc, num_dimm = 0;
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[1];
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struct ghes_edac_pvt *pvt;
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struct ghes_edac_dimm_fill dimm_fill;
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/*
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* We have only one logical memory controller to which all DIMMs belong.
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*/
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if (atomic_inc_return(&ghes_init) > 1)
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return 0;
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/* Get the number of DIMMs */
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dmi_walk(ghes_edac_count_dimms, &num_dimm);
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@ -424,26 +442,17 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
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layers[0].size = num_dimm;
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layers[0].is_virt_csrow = true;
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/*
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* We need to serialize edac_mc_alloc() and edac_mc_add_mc(),
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* to avoid duplicated memory controller numbers
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*/
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mutex_lock(&ghes_edac_lock);
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mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers,
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sizeof(*pvt));
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
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if (!mci) {
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pr_info("Can't allocate memory for EDAC data\n");
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mutex_unlock(&ghes_edac_lock);
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return -ENOMEM;
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}
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pvt = mci->pvt_info;
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memset(pvt, 0, sizeof(*pvt));
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list_add_tail(&pvt->list, &ghes_reglist);
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pvt->ghes = ghes;
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pvt->mci = mci;
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mci->pdev = dev;
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ghes_pvt = mci->pvt_info;
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ghes_pvt->ghes = ghes;
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ghes_pvt->mci = mci;
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mci->pdev = dev;
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mci->mtype_cap = MEM_FLAG_EMPTY;
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mci->edac_ctl_cap = EDAC_FLAG_NONE;
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mci->edac_cap = EDAC_FLAG_NONE;
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@ -451,36 +460,23 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
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mci->ctl_name = "ghes_edac";
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mci->dev_name = "ghes";
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if (!ghes_edac_mc_num) {
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if (!fake) {
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pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
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pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
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pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
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pr_info("If you find incorrect reports, please contact your hardware vendor\n");
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pr_info("to correct its BIOS.\n");
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pr_info("This system has %d DIMM sockets.\n",
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num_dimm);
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} else {
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pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
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pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
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pr_info("work on such system. Use this driver with caution\n");
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}
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if (!fake) {
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pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
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pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
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pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
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pr_info("If you find incorrect reports, please contact your hardware vendor\n");
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pr_info("to correct its BIOS.\n");
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pr_info("This system has %d DIMM sockets.\n", num_dimm);
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} else {
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pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
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pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
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pr_info("work on such system. Use this driver with caution\n");
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}
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if (!fake) {
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/*
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* Fill DIMM info from DMI for the memory controller #0
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*
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* Keep it in blank for the other memory controllers, as
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* there's no reliable way to properly credit each DIMM to
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* the memory controller, as different BIOSes fill the
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* DMI bank location fields on different ways
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*/
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if (!ghes_edac_mc_num) {
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dimm_fill.count = 0;
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dimm_fill.mci = mci;
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dmi_walk(ghes_edac_dmidecode, &dimm_fill);
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}
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dimm_fill.count = 0;
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dimm_fill.mci = mci;
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dmi_walk(ghes_edac_dmidecode, &dimm_fill);
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} else {
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struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
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mci->n_layers, 0, 0, 0);
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@ -496,26 +492,16 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
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if (rc < 0) {
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pr_info("Can't register at EDAC core\n");
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edac_mc_free(mci);
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mutex_unlock(&ghes_edac_lock);
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return -ENODEV;
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}
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ghes_edac_mc_num++;
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mutex_unlock(&ghes_edac_lock);
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return 0;
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}
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void ghes_edac_unregister(struct ghes *ghes)
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{
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struct mem_ctl_info *mci;
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struct ghes_edac_pvt *pvt, *tmp;
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list_for_each_entry_safe(pvt, tmp, &ghes_reglist, list) {
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if (ghes == pvt->ghes) {
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mci = pvt->mci;
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edac_mc_del_mc(mci->pdev);
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edac_mc_free(mci);
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list_del(&pvt->list);
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}
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}
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mci = ghes_pvt->mci;
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edac_mc_del_mc(mci->pdev);
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edac_mc_free(mci);
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}
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