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drm/i915/fbc: fix FBC_COMPRESSION_MASK on BDW+

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Its size is 11:0 instead of 10:0. Found by inspecting the spec. I'm
not aware of any real-world IGT failures caused by this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1477065346-13736-2-git-send-email-paulo.r.zanoni@intel.com
This commit is contained in:
Paulo Zanoni 2016-10-21 13:55:46 -02:00
parent 79f2624b1b
commit 0fc6a9dc94
2 changed files with 9 additions and 6 deletions
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10
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -1683,11 +1683,13 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
seq_printf(m, "FBC disabled: %s\n", seq_printf(m, "FBC disabled: %s\n",
dev_priv->fbc.no_fbc_reason); dev_priv->fbc.no_fbc_reason);
if (intel_fbc_is_active(dev_priv) && if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
INTEL_GEN(dev_priv) >= 7) uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
BDW_FBC_COMPRESSION_MASK :
IVB_FBC_COMPRESSION_MASK;
seq_printf(m, "Compressing: %s\n", seq_printf(m, "Compressing: %s\n",
yesno(I915_READ(FBC_STATUS2) & yesno(I915_READ(FBC_STATUS2) & mask));
FBC_COMPRESSION_MASK)); }
mutex_unlock(&dev_priv->fbc.lock); mutex_unlock(&dev_priv->fbc.lock);
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);

5
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2188,8 +2188,9 @@ enum skl_disp_power_wells {
#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
#define FBC_STATUS2 _MMIO(0x43214) #define FBC_STATUS2 _MMIO(0x43214)
#define FBC_COMPRESSION_MASK 0x7ff #define IVB_FBC_COMPRESSION_MASK 0x7ff
#define BDW_FBC_COMPRESSION_MASK 0xfff
#define FBC_LL_SIZE (1536) #define FBC_LL_SIZE (1536)