From 5bc94c992ad1dc97d0431512d02b41b7101a0457 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 13 Mar 2014 17:24:29 -0300 Subject: [PATCH 1/4] ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs Armada 38x SoCs have a 2 GHz fixed main PLL that is used to feed other clocks. This commit adds a DT representation of this clock through a fixed-clock compatible node. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1394742273-5113-3-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-38x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 812ce280b349..38fc3a0ba184 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -341,6 +341,13 @@ mdio { }; clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + /* 25 MHz reference crystal */ refclk: oscillator { compatible = "fixed-clock"; From d6bd4b4cb3207123c24f1cdc0dcb3ff97d4df604 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 13 Mar 2014 17:24:30 -0300 Subject: [PATCH 2/4] ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs The Armada 38x SoC family has a clock provider called "Core Divider", derived from the fixed 2 GHz main PLL clock. This is similar to the one on A370, A375 and AXP. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1394742273-5113-4-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-38x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 38fc3a0ba184..0ba4b48c640f 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -337,6 +337,14 @@ mdio { compatible = "marvell,orion-mdio"; reg = <0x72004 0x4>; }; + + coredivclk: clock@e4250 { + compatible = "marvell,armada-380-corediv-clock"; + reg = <0xe4250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; }; }; From 93b5577e500d39c2edf89e7c0c6020ff49761176 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 13 Mar 2014 17:24:31 -0300 Subject: [PATCH 3/4] ARM: mvebu: Add support for NAND controller in Armada 38x SoC The Armada 38x SoC family has a NAND controller, compatible with the controller in Armada 370/375/XP SoCs. Add support for it in the devicetree file. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1394742273-5113-5-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-38x.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 0ba4b48c640f..a064f59da02d 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -345,6 +345,16 @@ coredivclk: clock@e4250 { clocks = <&mainpll>; clock-output-names = "nand"; }; + + flash@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + clocks = <&coredivclk 0>; + status = "disabled"; + }; }; }; From 4de29e636946dbc97586de6136a3c496a55fd5e6 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 13 Mar 2014 17:24:32 -0300 Subject: [PATCH 4/4] ARM: mvebu: Enable NAND controller in Armada 385-DB The Armada 385-DB board has a NAND flash, so enable it in the devicetree and add the partitions as prepared in the factory images. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1394742273-5113-6-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-385-db.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 9a136428ec29..6828d77696a6 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -80,6 +80,27 @@ phy1: ethernet-phy@1 { reg = <1>; }; }; + + flash@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; }; pcie-controller {