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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-27 00:20:58 +07:00
b43: N-PHY: implement few random missing ops
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Rafał Miłecki
John W. Linville
parent
73d07a39ee
commit
0eff8fcd29
@ -78,6 +78,7 @@ enum b43_nphy_rssi_type {
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B43_NPHY_RSSI_TBD,
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};
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/* TODO: reorder functions */
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static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
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bool enable);
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static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
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@ -88,6 +89,7 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
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u16 value, u8 core, bool off);
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static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
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u16 value, u8 core);
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static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev);
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static inline bool b43_nphy_ipa(struct b43_wldev *dev)
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{
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@ -453,8 +455,14 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
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tmp = (tmp & 0xFF00) | bbmult;
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b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
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if (0)
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; /* TODO */
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if (b43_nphy_ipa(dev)) {
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u32 tmp32;
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u16 reg = (i == 0) ?
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B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
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tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, txpi[i]));
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b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
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b43_phy_set(dev, reg, 0x4);
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}
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}
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b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
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@ -463,6 +471,57 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
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b43_nphy_stay_in_carrier_search(dev, 0);
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}
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static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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const u32 *table = NULL;
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#if 0
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TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
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u32 rfpwr_offset;
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u8 pga_gain;
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int i;
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#endif
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if (phy->rev >= 3) {
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if (b43_nphy_ipa(dev)) {
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table = b43_nphy_get_ipa_gain_table(dev);
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} else {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
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if (phy->rev == 3)
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table = b43_ntab_tx_gain_rev3_5ghz;
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if (phy->rev == 4)
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table = b43_ntab_tx_gain_rev4_5ghz;
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else
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table = b43_ntab_tx_gain_rev5plus_5ghz;
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} else {
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table = b43_ntab_tx_gain_rev3plus_2ghz;
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}
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}
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} else {
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table = b43_ntab_tx_gain_rev0_1_2;
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}
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b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
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b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
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if (phy->rev >= 3) {
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#if 0
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nphy->gmval = (table[0] >> 16) & 0x7000;
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for (i = 0; i < 128; i++) {
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pga_gain = (table[i] >> 24) & 0xF;
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
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rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
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else
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rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
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b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
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rfpwr_offset);
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b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
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rfpwr_offset);
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}
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#endif
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}
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
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static void b43_radio_2055_setup(struct b43_wldev *dev,
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@ -1430,8 +1489,19 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
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static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
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{
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struct b43_phy_n *nphy = dev->phy.n;
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struct ssb_sprom *sprom = dev->dev->bus_sprom;
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/* TX to RX */
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u8 tx2rx_events[9] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
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u8 tx2rx_delays[9] = { 8, 4, 2, 2, 4, 4, 6, 1 };
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/* RX to TX */
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u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
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0x1F };
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u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
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u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
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u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
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u16 tmp16;
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u32 tmp32;
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@ -1449,7 +1519,22 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
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b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
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b43_phy_write(dev, 0x2AE, 0x000C);
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/* TODO */
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/* TX to RX */
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b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 9);
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/* RX to TX */
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if (b43_nphy_ipa(dev))
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b43_nphy_set_rf_sequence(dev, 1, rx2tx_events_ipa,
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rx2tx_delays_ipa, 9);
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if (nphy->hw_phyrxchain != 3 &&
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nphy->hw_phyrxchain != nphy->hw_phytxchain) {
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if (b43_nphy_ipa(dev)) {
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rx2tx_delays[5] = 59;
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rx2tx_delays[6] = 1;
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rx2tx_events[7] = 0x1F;
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}
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b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays, 9);
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}
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tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
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0x2 : 0x9C40;
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@ -1553,8 +1638,8 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
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if (sprom->boardflags2_lo & 0x100 &&
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dev->dev->board_type == 0x8B) {
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if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
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dev->dev->board_type == 0x8B) {
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delays1[0] = 0x1;
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delays1[5] = 0x14;
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}
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@ -2649,8 +2734,8 @@ static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
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{
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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if (dev->phy.rev >= 6) {
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/* TODO If the chip is 47162
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return txpwrctrl_tx_gain_ipa_rev5 */
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if (dev->dev->chip_id == 47162)
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return txpwrctrl_tx_gain_ipa_rev5;
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return txpwrctrl_tx_gain_ipa_rev6;
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} else if (dev->phy.rev >= 5) {
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return txpwrctrl_tx_gain_ipa_rev5;
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@ -3717,7 +3802,7 @@ int b43_phy_initn(struct b43_wldev *dev)
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b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
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b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
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if (sprom->boardflags2_lo & 0x100 ||
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if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
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(dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
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dev->dev->board_type == 0x8B))
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b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
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@ -3774,15 +3859,7 @@ int b43_phy_initn(struct b43_wldev *dev)
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b43_nphy_tx_power_fix(dev);
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/* TODO N PHY TX Power Control Idle TSSI */
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/* TODO N PHY TX Power Control Setup */
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if (phy->rev >= 3) {
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/* TODO */
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} else {
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b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
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b43_ntab_tx_gain_rev0_1_2);
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b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
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b43_ntab_tx_gain_rev0_1_2);
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}
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b43_nphy_tx_gain_table_upload(dev);
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if (nphy->phyrxchain != 3)
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b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
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@ -764,6 +764,8 @@ struct b43_phy_n {
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u8 cal_orig_pwr_idx[2];
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u8 measure_hold;
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u8 phyrxchain;
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u8 hw_phyrxchain;
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u8 hw_phytxchain;
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u8 perical;
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u32 deaf_count;
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u32 rxcalparams;
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