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clk: imx6sl: ensure MMDC CH0 handshake is bypassed

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Same as other i.MX6 SoCs, ensure unused MMDC channel's
handshake is bypassed, this is to make sure no request
signal will be generated when periphe_clk_sel is changed
or SRC warm reset is triggered.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Anson Huang 2018-11-30 07:23:47 +00:00 committed by Stephen Boyd
parent ea662d2f80
commit 0efcc2c0fd
1 changed files with 6 additions and 0 deletions
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6
drivers/clk/imx/clk-imx6sl.c
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@ -17,6 +17,8 @@
#include "clk.h" #include "clk.h"
#define CCDR 0x4
#define BM_CCM_CCDR_MMDC_CH0_MASK (1 << 17)
#define CCSR 0xc #define CCSR 0xc
#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) #define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
#define CACRR 0x10 #define CACRR 0x10
@ -411,6 +413,10 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
/* Ensure the MMDC CH0 handshake is bypassed */
writel_relaxed(readl_relaxed(base + CCDR) |
BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
imx_check_clocks(clks, ARRAY_SIZE(clks)); imx_check_clocks(clks, ARRAY_SIZE(clks));
clk_data.clks = clks; clk_data.clks = clks;