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Qualcomm Device Tree Changes for v4.14

Browse Source 
* Fixup XO, timer nodes, and pinctrl on IPQ4019
 * Add IPQ4019 RNG and wifi blocks
 * Update MSM8974 coresight node
 * Add IPQ8074 bindings
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Merge tag 'qcom-dts-for-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt

Pull "Qualcomm Device Tree Changes for v4.14" from Andy Gross:

* Fixup XO, timer nodes, and pinctrl on IPQ4019
* Add IPQ4019 RNG and wifi blocks
* Update MSM8974 coresight node
* Add IPQ8074 bindings

* tag 'qcom-dts-for-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  ARM: dts: qcom: add and enable both wifi blocks on the IPQ4019
  ARM: dts: qcom-msm8974: dts: Update coresight replicator
  ARM: dts: qcom: add pseudo random number generator on the IPQ4019
  ARM: dts: ipq4019: Move xo and timer nodes to SoC dtsi
  ARM: dts: ipq4019: Fix pinctrl node name
  dt-bindings: qcom: Add IPQ8074 bindings
This commit is contained in:
Arnd Bergmann 2017-08-16 23:32:28 +02:00
commit 0ee72c9f25
4 changed files with 122 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/qcom.txt
View File

@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
msm8994
msm8996
mdm9615
ipq8074
The 'board' element must be one of the following strings:
@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
dragonboard
mtp
sbc
hk01
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same

29
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
View File

@ -20,27 +20,12 @@ / {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
clocks {
xo: xo {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
};
soc {
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <48000000>;
rng@22000 {
status = "ok";
};
pinctrl@0x01000000 {
pinctrl@1000000 {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
@ -108,5 +93,13 @@ crypto@8e3a000 {
watchdog@b017000 {
status = "ok";
};
wifi@a000000 {
status = "ok";
};
wifi@a800000 {
status = "ok";
};
};
};

109
arch/arm/boot/dts/qcom-ipq4019.dtsi
View File

@ -96,6 +96,21 @@ sleep_clk: sleep_clk {
clock-frequency = <32768>;
#clock-cells = <0>;
};
xo: xo {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <48000000>;
};
soc {
@ -119,7 +134,15 @@ gcc: clock-controller@1800000 {
reg = <0x1800000 0x60000>;
};
tlmm: pinctrl@0x01000000 {
rng@22000 {
compatible = "qcom,prng";
reg = <0x22000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
status = "disabled";
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
@ -269,5 +292,89 @@ restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
resets = <&gcc WIFI0_CPU_INIT_RESET>,
<&gcc WIFI0_RADIO_SRIF_RESET>,
<&gcc WIFI0_RADIO_WARM_RESET>,
<&gcc WIFI0_RADIO_COLD_RESET>,
<&gcc WIFI0_CORE_WARM_RESET>,
<&gcc WIFI0_CORE_COLD_RESET>;
reset-names = "wifi_cpu_init", "wifi_radio_srif",
"wifi_radio_warm", "wifi_radio_cold",
"wifi_core_warm", "wifi_core_cold";
clocks = <&gcc GCC_WCSS2G_CLK>,
<&gcc GCC_WCSS2G_REF_CLK>,
<&gcc GCC_WCSS2G_RTC_CLK>;
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
"wifi_wcss_rtc";
interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 168 IRQ_TYPE_NONE>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
"msi12", "msi13", "msi14", "msi15",
"legacy";
status = "disabled";
};
wifi1: wifi@a800000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa800000 0x200000>;
resets = <&gcc WIFI1_CPU_INIT_RESET>,
<&gcc WIFI1_RADIO_SRIF_RESET>,
<&gcc WIFI1_RADIO_WARM_RESET>,
<&gcc WIFI1_RADIO_COLD_RESET>,
<&gcc WIFI1_CORE_WARM_RESET>,
<&gcc WIFI1_CORE_COLD_RESET>;
reset-names = "wifi_cpu_init", "wifi_radio_srif",
"wifi_radio_warm", "wifi_radio_cold",
"wifi_core_warm", "wifi_core_cold";
clocks = <&gcc GCC_WCSS5G_CLK>,
<&gcc GCC_WCSS5G_REF_CLK>,
<&gcc GCC_WCSS5G_RTC_CLK>;
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
"wifi_wcss_rtc";
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 169 IRQ_TYPE_NONE>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
"msi12", "msi13", "msi14", "msi15",
"legacy";
status = "disabled";
};
};
};

2
arch/arm/boot/dts/qcom-msm8974.dtsi
View File

@ -779,7 +779,7 @@ tpiu_in: endpoint {
};
replicator@fc31c000 {
compatible = "qcom,coresight-replicator1x", "arm,primecell";
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0xfc31c000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;