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drm/amd/display: fix clk_mgr naming
clk_mgr is called dccg in dc_state, this change fixes that Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1399,7 +1399,7 @@ static enum dc_status enable_link_dp(
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pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
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link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
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state->dccg->funcs->update_clocks(state->dccg, state, false);
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state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
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dp_enable_link_phy(
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link,
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@ -2064,7 +2064,7 @@ void dc_resource_state_construct(
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const struct dc *dc,
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struct dc_state *dst_ctx)
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{
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dst_ctx->dccg = dc->res_pool->clk_mgr;
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dst_ctx->clk_mgr = dc->res_pool->clk_mgr;
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}
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/**
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@ -1166,8 +1166,8 @@ static void build_audio_output(
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
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pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
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audio_output->pll_info.dp_dto_source_clock_in_khz =
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state->dccg->funcs->get_dp_ref_clk_frequency(
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state->dccg);
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state->clk_mgr->funcs->get_dp_ref_clk_frequency(
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state->clk_mgr);
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}
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audio_output->pll_info.feed_back_divider =
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@ -301,7 +301,7 @@ struct dc_state {
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struct dcn_bw_internal_vars dcn_bw_vars;
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#endif
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struct clk_mgr *dccg;
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struct clk_mgr *clk_mgr;
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struct {
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bool full_update_needed : 1;
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