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drm/i915: Implement Wa_1607090982

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SIMD16 with Src0 scalar might conflict between Src1/Src2 and cause
GRF read issue. Workaround this issue by setting bit 14 in 0xe4f4
which will disable early read/src swap of Src0.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200207155138.30978-2-mika.kuoppala@linux.intel.com
This commit is contained in:
Mika Kuoppala 2020-02-07 17:51:38 +02:00 committed by Chris Wilson
parent 561db8296d
commit 0db1a5f870
2 changed files with 5 additions and 0 deletions
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3
drivers/gpu/drm/i915/gt/intel_workarounds.c
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@ -598,6 +598,9 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
/* Wa_1606931601:tgl */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
}
static void

2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -9148,6 +9148,8 @@ enum {
#define DISABLE_EARLY_EOT (1 << 1)
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
#define GEN12_DISABLE_EARLY_READ BIT(14)
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)