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x86: more header fixes
Summary: Add missing include guards for some x86 headers. This has only had the most rudimentary testing, but is hopefully obviously correct. Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -1,4 +1,5 @@
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#ifndef _ASM_SECCOMP_H
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#define _ASM_SECCOMP_H
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#include <linux/thread_info.h>
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@ -3,6 +3,9 @@
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* Based on code
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* Copyright 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#ifndef __ASM_X86_32_SUSPEND_H
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#define __ASM_X86_32_SUSPEND_H
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#include <asm/desc.h>
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#include <asm/i387.h>
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@ -44,3 +47,5 @@ static inline void acpi_save_register_state(unsigned long return_point)
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/* routines for saving/restoring kernel state */
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extern int acpi_save_state_mem(void);
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#endif
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#endif /* __ASM_X86_32_SUSPEND_H */
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@ -1,3 +1,6 @@
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#ifndef ASM_X86__XOR_32_H
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#define ASM_X86__XOR_32_H
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/*
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* Optimized RAID-5 checksumming functions for MMX and SSE.
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*
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@ -881,3 +884,5 @@ do { \
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deals with a load to a line that is being prefetched. */
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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(cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
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#endif /* ASM_X86__XOR_32_H */
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@ -1,3 +1,6 @@
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#ifndef ASM_X86__XOR_64_H
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#define ASM_X86__XOR_64_H
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/*
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* Optimized RAID-5 checksumming functions for MMX and SSE.
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*
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@ -354,3 +357,5 @@ do { \
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse)
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#endif /* ASM_X86__XOR_64_H */
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