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clk: renesas: cpg-mssr: Add support for fixed rate clocks

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Add support for defining fixed rate clocks, to be used for on-chip
oscillators.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2018-07-11 13:47:28 +02:00
parent 3a251270e6
commit 0d2602d750
2 changed files with 8 additions and 0 deletions
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5
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
}
break;
case CLK_TYPE_FR:
clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
core->mult);
break;
default:
if (info->cpg_clk_register)
clk = info->cpg_clk_register(dev, core, info,

3
drivers/clk/renesas/renesas-cpg-mssr.h
View File

@ -38,6 +38,7 @@ enum clk_types {
CLK_TYPE_FF, /* Fixed Factor Clock */
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
CLK_TYPE_FR, /* Fixed Rate Clock */
/* Custom definitions start here */
CLK_TYPE_CUSTOM,
@ -56,6 +57,8 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
#define DEF_RATE(_name, _id, _rate) \
DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
/*
* Definitions of Module Clocks