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arm64: dts: sdm845: Add lpasscc node
This adds the low pass audio clock controller node to sdm845 based on the example in the bindings. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> [bjorn: Disabled lpasscc node, as it's normally protected] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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@ -347,7 +347,9 @@ vreg_s3c_0p6: smps3 {
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&gcc {
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protected-clocks = <GCC_QSPI_CORE_CLK>,
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<GCC_QSPI_CORE_CLK_SRC>,
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<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
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<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
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<GCC_LPASS_Q6_AXI_CLK>,
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<GCC_LPASS_SWAY_CLK>;
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};
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&i2c10 {
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@ -7,6 +7,7 @@
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,lpass-sdm845.h>
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#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,videocc-sdm845.h>
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@ -2008,6 +2009,14 @@ apps_smmu: iommu@15000000 {
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
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};
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lpasscc: clock-controller@17014000 {
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compatible = "qcom,sdm845-lpasscc";
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reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
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reg-names = "cc", "qdsp6ss";
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#clock-cells = <1>;
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status = "disabled";
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};
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apss_shared: mailbox@17990000 {
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compatible = "qcom,sdm845-apss-shared";
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reg = <0x17990000 0x1000>;
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