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KVM: x86: do not attempt TSC synchronization on guest writes
KVM special-cases writes to MSR_IA32_TSC so that all CPUs have the same base for the TSC. This logic is complicated, and we do not want it to have any effect once the VM is started. In particular, if any guest started to synchronize its TSCs with writes to MSR_IA32_TSC rather than MSR_IA32_TSC_ADJUST, the additional effect of kvm_write_tsc code would be uncharted territory. Therefore, this patch makes writes to MSR_IA32_TSC behave essentially the same as writes to MSR_IA32_TSC_ADJUST when they come from the guest. A new selftest (which passes both before and after the patch) checks the current semantics of writes to MSR_IA32_TSC and MSR_IA32_TSC_ADJUST originating from both the host and the guest. Upcoming work to remove the special side effects of host-initiated writes to MSR_IA32_TSC and MSR_IA32_TSC_ADJUST will be able to build onto this test, adjusting the host side to use the new APIs and achieve the same effect. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
a7d5c7ce41
commit
0c899c25d7
@ -2107,12 +2107,6 @@ static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
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#endif
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}
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static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
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{
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u64 curr_offset = vcpu->arch.l1_tsc_offset;
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vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
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}
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/*
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* Multiply tsc by a fixed point number represented by ratio.
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*
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@ -2174,14 +2168,13 @@ static inline bool kvm_check_tsc_unstable(void)
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return check_tsc_unstable();
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}
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void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
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static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
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{
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struct kvm *kvm = vcpu->kvm;
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u64 offset, ns, elapsed;
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unsigned long flags;
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bool matched;
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bool already_matched;
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u64 data = msr->data;
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bool synchronizing = false;
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raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
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@ -2190,7 +2183,7 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
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elapsed = ns - kvm->arch.last_tsc_nsec;
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if (vcpu->arch.virtual_tsc_khz) {
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if (data == 0 && msr->host_initiated) {
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if (data == 0) {
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/*
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* detection of vcpu initialization -- need to sync
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* with other vCPUs. This particularly helps to keep
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@ -2260,9 +2253,6 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
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vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
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vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
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if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
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update_ia32_tsc_adjust_msr(vcpu, offset);
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kvm_vcpu_write_tsc_offset(vcpu, offset);
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raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
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@ -2277,8 +2267,6 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
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spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
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}
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EXPORT_SYMBOL_GPL(kvm_write_tsc);
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static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
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s64 adjustment)
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{
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@ -3073,7 +3061,13 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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vcpu->arch.msr_ia32_power_ctl = data;
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break;
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case MSR_IA32_TSC:
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kvm_write_tsc(vcpu, msr_info);
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if (msr_info->host_initiated) {
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kvm_synchronize_tsc(vcpu, data);
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} else {
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u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
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adjust_tsc_offset_guest(vcpu, adj);
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vcpu->arch.ia32_tsc_adjust_msr += adj;
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}
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break;
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case MSR_IA32_XSS:
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if (!msr_info->host_initiated &&
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@ -9839,7 +9833,6 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
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void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
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{
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struct msr_data msr;
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struct kvm *kvm = vcpu->kvm;
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kvm_hv_vcpu_postcreate(vcpu);
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@ -9847,10 +9840,7 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
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if (mutex_lock_killable(&vcpu->mutex))
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return;
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vcpu_load(vcpu);
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msr.data = 0x0;
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msr.index = MSR_IA32_TSC;
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msr.host_initiated = true;
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kvm_write_tsc(vcpu, &msr);
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kvm_synchronize_tsc(vcpu, 0);
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vcpu_put(vcpu);
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/* poll control enabled by default */
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@ -55,6 +55,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/vmx_set_nested_state_test
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TEST_GEN_PROGS_x86_64 += x86_64/vmx_tsc_adjust_test
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TEST_GEN_PROGS_x86_64 += x86_64/xss_msr_test
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TEST_GEN_PROGS_x86_64 += x86_64/debug_regs
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TEST_GEN_PROGS_x86_64 += x86_64/tsc_msrs_test
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TEST_GEN_PROGS_x86_64 += x86_64/user_msr_test
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TEST_GEN_PROGS_x86_64 += clear_dirty_log_test
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TEST_GEN_PROGS_x86_64 += demand_paging_test
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168
tools/testing/selftests/kvm/x86_64/tsc_msrs_test.c
Normal file
168
tools/testing/selftests/kvm/x86_64/tsc_msrs_test.c
Normal file
@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Tests for MSR_IA32_TSC and MSR_IA32_TSC_ADJUST.
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*
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* Copyright (C) 2020, Red Hat, Inc.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "kvm_util.h"
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#include "processor.h"
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#define VCPU_ID 0
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#define UNITY (1ull << 30)
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#define HOST_ADJUST (UNITY * 64)
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#define GUEST_STEP (UNITY * 4)
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#define ROUND(x) ((x + UNITY / 2) & -UNITY)
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#define rounded_rdmsr(x) ROUND(rdmsr(x))
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#define rounded_host_rdmsr(x) ROUND(vcpu_get_msr(vm, 0, x))
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#define GUEST_ASSERT_EQ(a, b) do { \
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__typeof(a) _a = (a); \
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__typeof(b) _b = (b); \
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if (_a != _b) \
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ucall(UCALL_ABORT, 4, \
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"Failed guest assert: " \
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#a " == " #b, __LINE__, _a, _b); \
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} while(0)
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static void guest_code(void)
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{
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u64 val = 0;
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/* Guest: writes to MSR_IA32_TSC affect both MSRs. */
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val = 1ull * GUEST_STEP;
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wrmsr(MSR_IA32_TSC, val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/* Guest: writes to MSR_IA32_TSC_ADJUST affect both MSRs. */
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GUEST_SYNC(2);
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val = 2ull * GUEST_STEP;
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wrmsr(MSR_IA32_TSC_ADJUST, val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/* Host: setting the TSC offset. */
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GUEST_SYNC(3);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/*
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* Guest: writes to MSR_IA32_TSC_ADJUST do not destroy the
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* host-side offset and affect both MSRs.
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*/
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GUEST_SYNC(4);
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val = 3ull * GUEST_STEP;
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wrmsr(MSR_IA32_TSC_ADJUST, val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/*
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* Guest: writes to MSR_IA32_TSC affect both MSRs, so the host-side
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* offset is now visible in MSR_IA32_TSC_ADJUST.
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*/
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GUEST_SYNC(5);
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val = 4ull * GUEST_STEP;
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wrmsr(MSR_IA32_TSC, val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
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GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val - HOST_ADJUST);
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GUEST_DONE();
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}
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static void run_vcpu(struct kvm_vm *vm, uint32_t vcpuid, int stage)
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{
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struct ucall uc;
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vcpu_args_set(vm, vcpuid, 1, vcpuid);
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vcpu_ioctl(vm, vcpuid, KVM_RUN, NULL);
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switch (get_ucall(vm, vcpuid, &uc)) {
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case UCALL_SYNC:
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TEST_ASSERT(!strcmp((const char *)uc.args[0], "hello") &&
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uc.args[1] == stage + 1, "Stage %d: Unexpected register values vmexit, got %lx",
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stage + 1, (ulong)uc.args[1]);
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return;
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case UCALL_DONE:
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return;
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case UCALL_ABORT:
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TEST_ASSERT(false, "%s at %s:%ld\n" \
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"\tvalues: %#lx, %#lx", (const char *)uc.args[0],
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__FILE__, uc.args[1], uc.args[2], uc.args[3]);
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default:
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TEST_ASSERT(false, "Unexpected exit: %s",
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exit_reason_str(vcpu_state(vm, vcpuid)->exit_reason));
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}
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}
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int main(void)
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{
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struct kvm_vm *vm;
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uint64_t val;
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vm = vm_create_default(VCPU_ID, 0, guest_code);
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vcpu_set_cpuid(vm, VCPU_ID, kvm_get_supported_cpuid());
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val = 0;
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/* Guest: writes to MSR_IA32_TSC affect both MSRs. */
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run_vcpu(vm, VCPU_ID, 1);
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val = 1ull * GUEST_STEP;
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/* Guest: writes to MSR_IA32_TSC_ADJUST affect both MSRs. */
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run_vcpu(vm, VCPU_ID, 2);
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val = 2ull * GUEST_STEP;
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/*
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* Host: writes to MSR_IA32_TSC set the host-side offset
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* and therefore do not change MSR_IA32_TSC_ADJUST.
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*/
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vcpu_set_msr(vm, 0, MSR_IA32_TSC, HOST_ADJUST + val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);
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run_vcpu(vm, VCPU_ID, 3);
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/* Host: writes to MSR_IA32_TSC_ADJUST do not modify the TSC. */
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vcpu_set_msr(vm, 0, MSR_IA32_TSC_ADJUST, UNITY * 123456);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
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ASSERT_EQ(vcpu_get_msr(vm, 0, MSR_IA32_TSC_ADJUST), UNITY * 123456);
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/* Restore previous value. */
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vcpu_set_msr(vm, 0, MSR_IA32_TSC_ADJUST, val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/*
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* Guest: writes to MSR_IA32_TSC_ADJUST do not destroy the
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* host-side offset and affect both MSRs.
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*/
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run_vcpu(vm, VCPU_ID, 4);
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val = 3ull * GUEST_STEP;
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);
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/*
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* Guest: writes to MSR_IA32_TSC affect both MSRs, so the host-side
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* offset is now visible in MSR_IA32_TSC_ADJUST.
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*/
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run_vcpu(vm, VCPU_ID, 5);
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val = 4ull * GUEST_STEP;
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
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ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val - HOST_ADJUST);
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kvm_vm_free(vm);
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return 0;
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}
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