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rtlwifi: rtl8192ee: Make driver support 64bits DMA.

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1. Both 32-bit and 64-bit use the same TX/RX buffer desc layout
2. Extend set_desc() and get_desc() to set and get 64-bit address
3. Remove directive DMA_IS_64BIT
4. Add module parameter to turn on 64-bit dma

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Cc: Yan-Hsuan Chuang <yhchuang@realtek.com>
Cc: Birming Chiu <birming@realtek.com>
Cc: Shaofu <shaofu@realtek.com>
Cc: Steven Ting <steventing@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Ping-Ke Shih 2017-09-29 14:47:53 -05:00 committed by Kalle Valo
parent ecf4000e0d
commit 0c07bd7457
27 changed files with 166 additions and 189 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
drivers/net/wireless/realtek/rtlwifi/pci.c
View File

@ -586,7 +586,7 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
skb = __skb_dequeue(&ring->queue);
pci_unmap_single(rtlpci->pdev,
rtlpriv->cfg->ops->
get_desc((u8 *)entry, true,
get_desc(hw, (u8 *)entry, true,
HW_DESC_TXBUFF_ADDR),
skb->len, PCI_DMA_TODEVICE);
@ -691,9 +691,10 @@ static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
return 0;
rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
if (rtlpriv->use_new_trx_flow) {
/* skb->cb may be 64 bit address */
rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
HW_DESC_RX_PREPARE,
(u8 *)&bufferaddress);
(u8 *)(dma_addr_t *)skb->cb);
} else {
rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
HW_DESC_RXBUFF_ADDR,
@ -798,7 +799,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
pdesc = &rtlpci->rx_ring[rxring_idx].desc[
rtlpci->rx_ring[rxring_idx].idx];
own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
false,
HW_DESC_OWN);
if (own) /* wait data to be filled by hardware */
@ -825,7 +826,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
(u8 *)buffer_desc,
hw_queue);
len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
HW_DESC_RXPKT_LEN);
if (skb->end - skb->tail > len) {
@ -1122,7 +1123,7 @@ static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
if (pskb) {
pci_unmap_single(rtlpci->pdev,
rtlpriv->cfg->ops->get_desc(
(u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
pskb->len, PCI_DMA_TODEVICE);
kfree_skb(pskb);
}
@ -1378,7 +1379,8 @@ static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
pci_unmap_single(rtlpci->pdev,
rtlpriv->cfg->
ops->get_desc((u8 *)entry, true,
ops->get_desc(hw, (u8 *)entry,
true,
HW_DESC_TXBUFF_ADDR),
skb->len, PCI_DMA_TODEVICE);
kfree_skb(skb);
@ -1507,7 +1509,7 @@ int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
for (i = 0; i < rtlpci->rxringcount; i++) {
entry = &rtlpci->rx_ring[rxring_idx].desc[i];
bufferaddress =
rtlpriv->cfg->ops->get_desc((u8 *)entry,
rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
false , HW_DESC_RXBUFF_ADDR);
memset((u8 *)entry , 0 ,
sizeof(*rtlpci->rx_ring
@ -1560,7 +1562,7 @@ int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
pci_unmap_single(rtlpci->pdev,
rtlpriv->cfg->ops->
get_desc((u8 *)
get_desc(hw, (u8 *)
entry,
true,
HW_DESC_TXBUFF_ADDR),
@ -1673,7 +1675,7 @@ static int rtl_pci_tx(struct ieee80211_hw *hw,
if (rtlpriv->use_new_trx_flow) {
ptx_bd_desc = &ring->buffer_desc[idx];
} else {
own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
true, HW_DESC_OWN);
if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
@ -2163,6 +2165,21 @@ static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
return ret;
}
static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
{
u8 value;
pci_read_config_byte(pdev, 0x719, &value);
/* 0x719 Bit5 is DMA64 bit fetch. */
if (dma64)
value |= BIT(5);
else
value &= ~BIT(5);
pci_write_config_byte(pdev, 0x719, value);
}
int rtl_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
@ -2181,13 +2198,25 @@ int rtl_pci_probe(struct pci_dev *pdev,
return err;
}
if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
WARN_ONCE(true,
"Unable to obtain 64bit DMA for consistent allocations\n");
err = -ENOMEM;
goto fail1;
}
platform_enable_dma64(pdev, true);
} else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
WARN_ONCE(true,
"rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
err = -ENOMEM;
goto fail1;
}
platform_enable_dma64(pdev, false);
}
pci_set_master(pdev);

10
drivers/net/wireless/realtek/rtlwifi/pci.h
View File

@ -143,13 +143,7 @@ struct rtl_pci_capabilities_header {
* RX wifi info == RX descriptor in old flow
*/
struct rtl_tx_buffer_desc {
#if (RTL8192EE_SEG_NUM == 2)
u32 dword[2*(DMA_IS_64BIT + 1)*8]; /*seg = 8*/
#elif (RTL8192EE_SEG_NUM == 1)
u32 dword[2*(DMA_IS_64BIT + 1)*4]; /*seg = 4*/
#elif (RTL8192EE_SEG_NUM == 0)
u32 dword[2*(DMA_IS_64BIT + 1)*2]; /*seg = 2*/
#endif
u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))];
} __packed;
struct rtl_tx_desc {
@ -157,7 +151,7 @@ struct rtl_tx_desc {
} __packed;
struct rtl_rx_buffer_desc { /*rx buffer desc*/
u32 dword[2];
u32 dword[4];
} __packed;
struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/

1
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c
View File

@ -99,6 +99,7 @@ static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
pci_unmap_single(rtlpci->pdev,
rtlpriv->cfg->ops->get_desc(
hw,
(u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
skb->len, PCI_DMA_TODEVICE);
kfree_skb(skb);

5
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c
View File

@ -786,7 +786,8 @@ void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
}
}
u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
u64 rtl88ee_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name)
{
u32 ret = 0;
@ -828,7 +829,7 @@ bool rtl88ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl88ee_get_desc(entry, true, HW_DESC_OWN);
u8 own = (u8)rtl88ee_get_desc(hw, entry, true, HW_DESC_OWN);
/*beacon packet will only use the first
*descriptor defautly,and the own may not

3
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h
View File

@ -782,7 +782,8 @@ bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
u8 *pdesc, struct sk_buff *skb);
void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
bool istx, u8 desc_name, u8 *val);
u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl88ee_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name);
bool rtl88ee_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);

5
drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c
View File

@ -697,7 +697,8 @@ void rtl92ce_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
}
}
u32 rtl92ce_get_desc(u8 *p_desc, bool istx, u8 desc_name)
u64 rtl92ce_get_desc(struct ieee80211_hw *hw, u8 *p_desc,
bool istx, u8 desc_name)
{
u32 ret = 0;
@ -740,7 +741,7 @@ bool rtl92ce_is_tx_desc_closed(struct ieee80211_hw *hw,
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl92ce_get_desc(entry, true, HW_DESC_OWN);
u8 own = (u8)rtl92ce_get_desc(hw, entry, true, HW_DESC_OWN);
/*beacon packet will only use the first
*descriptor defautly,and the own may not

3
drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h
View File

@ -718,7 +718,8 @@ bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
u8 *pdesc, struct sk_buff *skb);
void rtl92ce_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 rtl92ce_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl92ce_get_desc(struct ieee80211_hw *hw, u8 *p_desc,
bool istx, u8 desc_name);
bool rtl92ce_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl92ce_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);

2
drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c
View File

@ -490,7 +490,7 @@ static bool _rtl92d_cmd_send_packet(struct ieee80211_hw *hw,
spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
pdesc = &ring->desc[idx];
/* discard output from call below */
rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN);
rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
__skb_queue_tail(&ring->queue, skb);
spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);

3
drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c
View File

@ -821,7 +821,8 @@ void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
}
}
u32 rtl92de_get_desc(u8 *p_desc, bool istx, u8 desc_name)
u64 rtl92de_get_desc(struct ieee80211_hw *hw,
u8 *p_desc, bool istx, u8 desc_name)
{
u32 ret = 0;

3
drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h
View File

@ -735,7 +735,8 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw,
u8 *pdesc, struct sk_buff *skb);
void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 rtl92de_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl92de_get_desc(struct ieee80211_hw *hw,
u8 *p_desc, bool istx, u8 desc_name);
void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
bool b_firstseg, bool b_lastseg,

31
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c
View File

@ -840,6 +840,31 @@ static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
/* Set TCR register */
rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
/* Set TX/RX descriptor physical address -- HI part */
if (!rtlpriv->cfg->mod_params->dma64)
goto dma64_end;
rtl_write_dword(rtlpriv, REG_BCNQ_DESA + 4,
((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >>
32);
rtl_write_dword(rtlpriv, REG_MGQ_DESA + 4,
(u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma >> 32);
rtl_write_dword(rtlpriv, REG_VOQ_DESA + 4,
(u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma >> 32);
rtl_write_dword(rtlpriv, REG_VIQ_DESA + 4,
(u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma >> 32);
rtl_write_dword(rtlpriv, REG_BEQ_DESA + 4,
(u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma >> 32);
rtl_write_dword(rtlpriv, REG_BKQ_DESA + 4,
(u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma >> 32);
rtl_write_dword(rtlpriv, REG_HQ0_DESA + 4,
(u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma >> 32);
rtl_write_dword(rtlpriv, REG_RX_DESA + 4,
(u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma >> 32);
dma64_end:
/* Set TX/RX descriptor physical address(from OS API). */
rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
@ -913,15 +938,9 @@ static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,
TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
/*Rx*/
#if (DMA_IS_64BIT == 1)
rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
RX_DESC_NUM_92E |
((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);
#else
rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
RX_DESC_NUM_92E |
((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000);
#endif
rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);

3
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c
View File

@ -259,6 +259,7 @@ static struct rtl_mod_params rtl92ee_mod_params = {
.swctrl_lps = false,
.fwctrl_lps = true,
.msi_support = true,
.dma64 = false,
.debug_level = 0,
.debug_mask = 0,
};
@ -376,6 +377,7 @@ module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
module_param_named(dma64, rtl92ee_mod_params.dma64, bool, 0444);
module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
bool, 0444);
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
@ -383,6 +385,7 @@ MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");

49
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c
View File

@ -581,13 +581,9 @@ void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
u8 i = 0;
u16 real_desc_size = 0x28;
u16 append_early_mode_size = 0;
#if (RTL8192EE_SEG_NUM == 0)
u8 segmentnum = 2;
#elif (RTL8192EE_SEG_NUM == 1)
u8 segmentnum = 4;
#elif (RTL8192EE_SEG_NUM == 2)
u8 segmentnum = 8;
#endif
u8 segmentnum = 1 << (RTL8192EE_SEG_NUM + 1);
dma_addr_t desc_dma_addr;
bool dma64 = rtlpriv->cfg->mod_params->dma64;
tx_page_size = 2;
current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
@ -609,6 +605,10 @@ void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
psblen += 1;
}
/* tx desc addr */
desc_dma_addr = rtlpci->tx_ring[queue_index].dma +
(current_bd_desc * TX_DESC_SIZE);
/* Reset */
SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0);
SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0);
@ -618,17 +618,9 @@ void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
#if (DMA_IS_64BIT == 1)
SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(tx_bd_desc, i, 0);
#endif
SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, i, 0, dma64);
}
SET_TX_BUFF_DESC_LEN_1(tx_bd_desc, 0);
SET_TX_BUFF_DESC_AMSDU_1(tx_bd_desc, 0);
SET_TX_BUFF_DESC_LEN_2(tx_bd_desc, 0);
SET_TX_BUFF_DESC_AMSDU_2(tx_bd_desc, 0);
SET_TX_BUFF_DESC_LEN_3(tx_bd_desc, 0);
SET_TX_BUFF_DESC_AMSDU_3(tx_bd_desc, 0);
/* Clear all status */
CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
@ -643,14 +635,16 @@ void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
}
SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen);
SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc,
rtlpci->tx_ring[queue_index].dma +
(current_bd_desc * TX_DESC_SIZE));
SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc, desc_dma_addr);
SET_TX_BUFF_DESC_ADDR_HIGH_0(tx_bd_desc, ((u64)desc_dma_addr >> 32),
dma64);
SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
/* don't using extendsion mode. */
SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr);
SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, 1,
((u64)addr >> 32), dma64);
SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len));
SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len));
@ -918,6 +912,7 @@ void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
static bool over_run;
u32 tmp = 0;
u8 q_idx = *val;
bool dma64 = rtlpriv->cfg->mod_params->dma64;
if (istx) {
switch (desc_name) {
@ -982,7 +977,12 @@ void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
MAX_RECEIVE_BUFFER_SIZE +
RX_DESC_SIZE);
SET_RX_BUFFER_PHYSICAL_LOW(pdesc, *(u32 *)val);
SET_RX_BUFFER_PHYSICAL_LOW(pdesc, (*(dma_addr_t *)val) &
DMA_BIT_MASK(32));
SET_RX_BUFFER_PHYSICAL_HIGH(pdesc,
((u64)(*(dma_addr_t *)val)
>> 32),
dma64);
break;
case HW_DESC_RXERO:
SET_RX_DESC_EOR(pdesc, 1);
@ -996,9 +996,12 @@ void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
}
}
u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
u64 rtl92ee_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name)
{
u32 ret = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u64 ret = 0;
bool dma64 = rtlpriv->cfg->mod_params->dma64;
if (istx) {
switch (desc_name) {
@ -1007,6 +1010,8 @@ u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
break;
case HW_DESC_TXBUFF_ADDR:
ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1);
ret |= (u64)GET_TXBUFFER_DESC_ADDR_HIGH(pdesc, 1,
dma64) << 32;
break;
default:
WARN_ONCE(true,

124
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h
View File

@ -26,24 +26,6 @@
#ifndef __RTL92E_TRX_H__
#define __RTL92E_TRX_H__
#if (DMA_IS_64BIT == 1)
#if (RTL8192EE_SEG_NUM == 2)
#define TX_BD_DESC_SIZE 128
#elif (RTL8192EE_SEG_NUM == 1)
#define TX_BD_DESC_SIZE 64
#elif (RTL8192EE_SEG_NUM == 0)
#define TX_BD_DESC_SIZE 32
#endif
#else
#if (RTL8192EE_SEG_NUM == 2)
#define TX_BD_DESC_SIZE 64
#elif (RTL8192EE_SEG_NUM == 1)
#define TX_BD_DESC_SIZE 32
#elif (RTL8192EE_SEG_NUM == 0)
#define TX_BD_DESC_SIZE 16
#endif
#endif
#define TX_DESC_SIZE 64
#define RX_DRV_INFO_SIZE_UNIT 8
@ -331,28 +313,18 @@
SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+8, 0, 32, __val)
/* for Txfilldescroptor92ee, fill the desc content. */
#if (DMA_IS_64BIT == 1)
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 0, 16, __val)
SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 0, 16, __val)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 31, 1, __val)
SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 31, 1, __val)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+4, 0, 32, __val)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)\
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+8, 0, 32, __val)
SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32, __val)
#define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(pbd, off, val, dma64) \
(dma64 ? SET_BITS_TO_LE_4BYTE((pbd) + ((off) * 16) + 8, 0, 32, val) : 0)
#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
LE_BITS_TO_4BYTE(__pdesc+(__offset*16)+4, 0, 32)
#else
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 0, 16, __val)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 31, 1, __val)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8)+4, 0, 32, __val)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)
#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
LE_BITS_TO_4BYTE(__pdesc+(__offset*8)+4, 0, 32)
#endif
LE_BITS_TO_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32)
#define GET_TXBUFFER_DESC_ADDR_HIGH(pbd, off, dma64) \
(dma64 ? LE_BITS_TO_4BYTE((pbd) + ((off) * 16) + 8, 0, 32) : 0)
/* Dword 0 */
#define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val) \
@ -364,78 +336,11 @@
/* Dword 1 */
#define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 32, __val)
#if (DMA_IS_64BIT == 1)
SET_BITS_TO_LE_4BYTE((__pdesc) + 4, 0, 32, __val)
/* Dword 2 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 32, __val)
#define SET_TX_BUFF_DESC_ADDR_HIGH_0(bdesc, val, dma64) \
SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(bdesc, 0, val, dma64)
/* Dword 3 / RESERVED 0 */
/* Dword 4 */
#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
/* Dword 5 */
#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
/* Dword 6 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
/* Dword 7 / RESERVED 0 */
/* Dword 8 */
#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32, 31, 1, __val)
/* Dword 9 */
#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val)
/* Dword 10 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
/* Dword 11 / RESERVED 0 */
/* Dword 12 */
#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+48, 31, 1, __val)
/* Dword 13 */
#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+52, 0, 32, __val)
/* Dword 14 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+56, 0, 32, __val)
/* Dword 15 / RESERVED 0 */
#else
#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val)
/* Dword 2 */
#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 31, 1, __val)
/* Dword 3 */
#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 32, __val)
#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val)
/* Dword 4 */
#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
/* Dword 5 */
#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val)
/* Dword 6 */
#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 31, 1, __val)
/* Dword 7 */
#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val)
#endif
/* RX buffer */
@ -463,8 +368,8 @@
SET_BITS_TO_LE_4BYTE(__status+4, 0, 32, __val)
/* DWORD 2 */
#define SET_RX_BUFFER_PHYSICAL_HIGH(__status, __val) \
SET_BITS_TO_LE_4BYTE(__status+8, 0, 32, __val)
#define SET_RX_BUFFER_PHYSICAL_HIGH(__rx_status_desc, __val, dma64) \
(dma64 ? SET_BITS_TO_LE_4BYTE((__rx_status_desc) + 8, 0, 32, __val) : 0)
#define GET_RX_DESC_PKT_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 0, 14)
@ -850,7 +755,8 @@ bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl92ee_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name);
bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index);
void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,

2
drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
View File

@ -240,7 +240,7 @@ static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl92se_get_desc(entry, true, HW_DESC_OWN);
u8 own = (u8)rtl92se_get_desc(hw, entry, true, HW_DESC_OWN);
if (own)
return false;

3
drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c
View File

@ -610,7 +610,8 @@ void rtl92se_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
}
}
u32 rtl92se_get_desc(u8 *desc, bool istx, u8 desc_name)
u64 rtl92se_get_desc(struct ieee80211_hw *hw,
u8 *desc, bool istx, u8 desc_name)
{
u32 ret = 0;

3
drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.h
View File

@ -38,7 +38,8 @@ bool rtl92se_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
struct sk_buff *skb);
void rtl92se_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 rtl92se_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl92se_get_desc(struct ieee80211_hw *hw,
u8 *desc, bool istx, u8 desc_name);
void rtl92se_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
#endif

5
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c
View File

@ -643,7 +643,8 @@ void rtl8723e_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
}
}
u32 rtl8723e_get_desc(u8 *pdesc, bool istx, u8 desc_name)
u64 rtl8723e_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name)
{
u32 ret = 0;
@ -686,7 +687,7 @@ bool rtl8723e_is_tx_desc_closed(struct ieee80211_hw *hw,
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl8723e_get_desc(entry, true, HW_DESC_OWN);
u8 own = (u8)rtl8723e_get_desc(hw, entry, true, HW_DESC_OWN);
/**
*beacon packet will only use the first

3
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h
View File

@ -708,7 +708,8 @@ bool rtl8723e_rx_query_desc(struct ieee80211_hw *hw,
u8 *pdesc, struct sk_buff *skb);
void rtl8723e_set_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name, u8 *val);
u32 rtl8723e_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl8723e_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name);
bool rtl8723e_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl8723e_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);

1
drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c
View File

@ -60,6 +60,7 @@ static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
pci_unmap_single(rtlpci->pdev,
rtlpriv->cfg->ops->get_desc(
hw,
(u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
skb->len, PCI_DMA_TODEVICE);
kfree_skb(skb);

5
drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c
View File

@ -695,7 +695,8 @@ void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
}
}
u32 rtl8723be_get_desc(u8 *pdesc, bool istx, u8 desc_name)
u64 rtl8723be_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name)
{
u32 ret = 0;
@ -738,7 +739,7 @@ bool rtl8723be_is_tx_desc_closed(struct ieee80211_hw *hw,
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl8723be_get_desc(entry, true, HW_DESC_OWN);
u8 own = (u8)rtl8723be_get_desc(hw, entry, true, HW_DESC_OWN);
/*beacon packet will only use the first
*descriptor defautly,and the own may not

3
drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h
View File

@ -624,7 +624,8 @@ bool rtl8723be_rx_query_desc(struct ieee80211_hw *hw,
u8 *pdesc, struct sk_buff *skb);
void rtl8723be_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
bool istx, u8 desc_name, u8 *val);
u32 rtl8723be_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl8723be_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name);
bool rtl8723be_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl8723be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);

3
drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c
View File

@ -253,7 +253,8 @@ bool rtl8723_cmd_send_packet(struct ieee80211_hw *hw,
spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
pdesc = &ring->desc[0];
own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc, true, HW_DESC_OWN);
own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, true,
HW_DESC_OWN);
rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);

1
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
View File

@ -57,6 +57,7 @@ static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
pci_unmap_single(rtlpci->pdev,
rtlpriv->cfg->ops->get_desc(
hw,
(u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
skb->len, PCI_DMA_TODEVICE);
kfree_skb(skb);

5
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c
View File

@ -935,7 +935,8 @@ void rtl8821ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
}
}
u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
u64 rtl8821ae_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name)
{
u32 ret = 0;
@ -980,7 +981,7 @@ bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl8821ae_get_desc(entry, true, HW_DESC_OWN);
u8 own = (u8)rtl8821ae_get_desc(hw, entry, true, HW_DESC_OWN);
/**
*beacon packet will only use the first

3
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h
View File

@ -620,7 +620,8 @@ bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
u8 *pdesc, struct sk_buff *skb);
void rtl8821ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
bool istx, u8 desc_name, u8 *val);
u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name);
u64 rtl8821ae_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name);
bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);

11
drivers/net/wireless/realtek/rtlwifi/wifi.h
View File

@ -169,7 +169,7 @@ enum rtl8192c_h2c_cmd {
#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
#define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
#define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
#define DEL_SW_IDX_SZ 30
#define BAND_NUM 3
@ -177,8 +177,7 @@ enum rtl8192c_h2c_cmd {
/* For now, it's just for 8192ee
* but not OK yet, keep it 0
*/
#define DMA_IS_64BIT 0
#define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
#define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
enum rf_tx_num {
RF_1TX = 0,
@ -2162,7 +2161,8 @@ struct rtl_hal_ops {
enum led_ctl_mode ledaction);
void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name);
bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
@ -2261,6 +2261,9 @@ struct rtl_mod_params {
*/
bool msi_support;
/* default: 0 = dma 32 */
bool dma64;
/* default 0: 1 means disable */
bool disable_watchdog;