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drm/amd/display: get dal1.1 to run
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -275,7 +275,7 @@ struct dce_hwseq_registers {
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
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HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
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HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_),\
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HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
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HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
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HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
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HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh), \
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@ -784,7 +784,7 @@ static void oppn10_program_color_matrix(struct dcn10_opp *oppn10,
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}
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}
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void oppn10_set_output_csc_adjustment(
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static void oppn10_set_output_csc_adjustment(
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struct output_pixel_processor *opp,
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const struct out_csc_color_matrix *tbl_entry)
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{
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