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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: dts: Add the arasan mmc DTS entries for APm X-Gene v2 SoC
This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene v2 SoC platforms. Signed-off-by: Duc Dang <dhdang@apm.com>
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@ -70,3 +70,7 @@ &sgenet0 {
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&xgenet1 {
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&xgenet1 {
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status = "ok";
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status = "ok";
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};
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};
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&mmc0 {
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status = "ok";
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};
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@ -140,6 +140,40 @@ socplldiv2: socplldiv2 {
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clock-output-names = "socplldiv2";
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clock-output-names = "socplldiv2";
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};
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};
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ahbclk: ahbclk@1f2ac000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f2ac000 0x0 0x1000
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0x0 0x17000000 0x0 0x2000>;
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reg-names = "csr-reg", "div-reg";
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csr-offset = <0x0>;
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csr-mask = <0x1>;
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enable-offset = <0x8>;
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enable-mask = <0x1>;
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divider-offset = <0x164>;
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divider-width = <0x5>;
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divider-shift = <0x0>;
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clock-output-names = "ahbclk";
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};
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sdioclk: sdioclk@1f2ac000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f2ac000 0x0 0x1000
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0x0 0x17000000 0x0 0x2000>;
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reg-names = "csr-reg", "div-reg";
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csr-offset = <0x0>;
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csr-mask = <0x2>;
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enable-offset = <0x8>;
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enable-mask = <0x2>;
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divider-offset = <0x178>;
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divider-width = <0x8>;
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divider-shift = <0x0>;
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clock-output-names = "sdioclk";
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};
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pcie0clk: pcie0clk@1f2bc000 {
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pcie0clk: pcie0clk@1f2bc000 {
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compatible = "apm,xgene-device-clock";
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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#clock-cells = <1>;
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@ -224,6 +258,16 @@ sata3: sata@1a400000 {
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dma-coherent;
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dma-coherent;
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};
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};
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mmc0: mmc@1c000000 {
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compatible = "arasan,sdhci-4.9a";
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reg = <0x0 0x1c000000 0x0 0x100>;
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interrupts = <0x0 0x49 0x4>;
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dma-coherent;
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no-1-8-v;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&sdioclk 0>, <&ahbclk 0>;
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};
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sbgpio: sbgpio@17001000{
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sbgpio: sbgpio@17001000{
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compatible = "apm,xgene-gpio-sb";
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compatible = "apm,xgene-gpio-sb";
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reg = <0x0 0x17001000 0x0 0x400>;
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reg = <0x0 0x17001000 0x0 0x400>;
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