ARM: dts: rockchip: add clock-cells for usb phy nodes

Add the #clock-cells properties for the usbphy nodes as they
provide the pll-clocks now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Heiko Stuebner 2015-11-19 22:22:27 +01:00
parent df5ea01598
commit 0ace8217c2
3 changed files with 7 additions and 0 deletions

View File

@ -202,6 +202,7 @@ usbphy0: usb-phy0 {
reg = <0x17c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
};
usbphy1: usb-phy1 {
@ -209,6 +210,7 @@ usbphy1: usb-phy1 {
reg = <0x188>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
};
};

View File

@ -171,6 +171,7 @@ usbphy0: usb-phy0 {
reg = <0x10c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
};
usbphy1: usb-phy1 {
@ -178,6 +179,7 @@ usbphy1: usb-phy1 {
reg = <0x11c>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
};
};

View File

@ -968,6 +968,7 @@ usbphy0: usb-phy0 {
reg = <0x320>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
};
usbphy1: usb-phy1 {
@ -975,6 +976,7 @@ usbphy1: usb-phy1 {
reg = <0x334>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
};
usbphy2: usb-phy2 {
@ -982,6 +984,7 @@ usbphy2: usb-phy2 {
reg = <0x348>;
clocks = <&cru SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
};
};