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ARM: at91/pm_slowclock: create the procedure to handle the sdram self-refresh
To decrease the duplicated code, create the procedure to contain both activing and exiting the sdram self-refresh mode. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Sylvain Rochet <sylvain.rochet@finsecur.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Wenyou Yang
Nicolas Ferre
parent
d18c570ef3
commit
0ab285c2fa
@ -16,10 +16,10 @@
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#include <mach/hardware.h>
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#include <mach/at91_ramc.h>
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#define SRAMC_SELF_FRESH_ACTIVE 0x01
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#define SRAMC_SELF_FRESH_EXIT 0x00
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pmc .req r0
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sdramc .req r1
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ramc1 .req r2
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memctrl .req r3
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tmp1 .req r4
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tmp2 .req r5
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@ -75,78 +75,17 @@ ENTRY(at91_slow_clock)
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mov tmp1, #0
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mcr p15, 0, tmp1, c7, c10, 4
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cmp memctrl, #AT91_MEMCTRL_MC
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bne ddr_sr_enable
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str r0, .pmc_base
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str r1, .sramc_base
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str r2, .sramc1_base
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str r3, .memtype
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/*
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* at91rm9200 Memory controller
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*/
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/* Put SDRAM in self-refresh mode */
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mov tmp1, #1
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str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
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b sdr_sr_done
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/* Active the self-refresh mode */
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mov r0, #SRAMC_SELF_FRESH_ACTIVE
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bl at91_sramc_self_refresh
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/*
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* DDRSDR Memory controller
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*/
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ddr_sr_enable:
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cmp memctrl, #AT91_MEMCTRL_DDRSDR
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bne sdr_sr_enable
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ldr pmc, .pmc_base
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/* LPDDR1 --> force DDR2 mode during self-refresh */
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ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
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str tmp1, .saved_sam9_mdr
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bic tmp1, tmp1, #~AT91_DDRSDRC_MD
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cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
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biceq tmp1, tmp1, #AT91_DDRSDRC_MD
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orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
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streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
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/* prepare for DDRAM self-refresh mode */
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ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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str tmp1, .saved_sam9_lpr
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bic tmp1, #AT91_DDRSDRC_LPCB
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orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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/* figure out if we use the second ram controller */
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cmp ramc1, #0
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beq ddr_no_2nd_ctrl
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ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
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str tmp2, .saved_sam9_mdr1
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bic tmp2, tmp2, #~AT91_DDRSDRC_MD
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cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
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biceq tmp2, tmp2, #AT91_DDRSDRC_MD
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orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
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streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
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ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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str tmp2, .saved_sam9_lpr1
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bic tmp2, #AT91_DDRSDRC_LPCB
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orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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/* Enable DDRAM self-refresh mode */
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str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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ddr_no_2nd_ctrl:
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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b sdr_sr_done
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/*
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* SDRAMC Memory controller
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*/
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sdr_sr_enable:
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/* Enable SDRAM self-refresh mode */
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ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
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str tmp1, .saved_sam9_lpr
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bic tmp1, #AT91_SDRAMC_LPCB
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orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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sdr_sr_done:
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/* Save Master clock setting */
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ldr tmp1, [pmc, #AT91_PMC_MCKR]
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str tmp1, .saved_mckr
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@ -199,67 +138,162 @@ sdr_sr_done:
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/*
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* Restore master clock setting
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*/
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2: ldr tmp1, .saved_mckr
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ldr tmp1, .saved_mckr
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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/* Exit the self-refresh mode */
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mov r0, #SRAMC_SELF_FRESH_EXIT
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bl at91_sramc_self_refresh
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/* Restore registers, and return */
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ldmfd sp!, {r4 - r12, pc}
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ENDPROC(at91_slow_clock)
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/*
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* void at91_sramc_self_refresh(unsigned int is_active)
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*
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* @input param:
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* @r0: 1 - active self-refresh mode
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* 0 - exit self-refresh mode
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* register usage:
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* @r1: memory type
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* @r2: base address of the sram controller
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*/
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ENTRY(at91_sramc_self_refresh)
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ldr r1, .memtype
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ldr r2, .sramc_base
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cmp r1, #AT91_MEMCTRL_MC
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bne ddrc_sf
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/*
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* at91rm9200 Memory controller
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* Do nothing - self-refresh is automatically disabled.
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*/
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cmp memctrl, #AT91_MEMCTRL_MC
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beq ram_restored
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/*
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* DDRSDR Memory controller
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* For exiting the self-refresh mode, do nothing,
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* automatically exit the self-refresh mode.
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*/
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cmp memctrl, #AT91_MEMCTRL_DDRSDR
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bne sdr_en_restore
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq exit_sramc_sf
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/* Active SDRAM self-refresh mode */
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mov r3, #1
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str r3, [r2, #AT91RM9200_SDRAMC_SRR]
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b exit_sramc_sf
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ddrc_sf:
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cmp r1, #AT91_MEMCTRL_DDRSDR
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bne sdramc_sf
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/*
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* DDR Memory controller
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*/
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq ddrc_exit_sf
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/* LPDDR1 --> force DDR2 mode during self-refresh */
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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str r3, .saved_sam9_mdr
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bic r3, r3, #~AT91_DDRSDRC_MD
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cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq r3, [r2, #AT91_DDRSDRC_MDR]
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biceq r3, r3, #AT91_DDRSDRC_MD
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orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
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streq r3, [r2, #AT91_DDRSDRC_MDR]
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/* Active DDRC self-refresh mode */
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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str r3, .saved_sam9_lpr
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bic r3, r3, #AT91_DDRSDRC_LPCB
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orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR]
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/* If using the 2nd ddr controller */
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ldr r2, .sramc1_base
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cmp r2, #0
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beq no_2nd_ddrc
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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str r3, .saved_sam9_mdr1
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bic r3, r3, #~AT91_DDRSDRC_MD
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cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq r3, [r2, #AT91_DDRSDRC_MDR]
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biceq r3, r3, #AT91_DDRSDRC_MD
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orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
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streq r3, [r2, #AT91_DDRSDRC_MDR]
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/* Active DDRC self-refresh mode */
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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str r3, .saved_sam9_lpr1
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bic r3, r3, #AT91_DDRSDRC_LPCB
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orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR]
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no_2nd_ddrc:
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b exit_sramc_sf
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ddrc_exit_sf:
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/* Restore MDR in case of LPDDR1 */
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ldr tmp1, .saved_sam9_mdr
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str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
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ldr r3, .saved_sam9_mdr
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str r3, [r2, #AT91_DDRSDRC_MDR]
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/* Restore LPR on AT91 with DDRAM */
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_DDRSDRC_LPR]
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/* if we use the second ram controller */
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cmp ramc1, #0
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ldrne tmp2, .saved_sam9_mdr1
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strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
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ldrne tmp2, .saved_sam9_lpr1
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strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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/* If using the 2nd ddr controller */
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ldr r2, .sramc1_base
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cmp r2, #0
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ldrne r3, .saved_sam9_mdr1
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strne r3, [r2, #AT91_DDRSDRC_MDR]
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ldrne r3, .saved_sam9_lpr1
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strne r3, [r2, #AT91_DDRSDRC_LPR]
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b ram_restored
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b exit_sramc_sf
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/*
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* SDRAMC Memory controller
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*/
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sdr_en_restore:
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/* Restore LPR on AT91 with SDRAM */
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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sdramc_sf:
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq sdramc_exit_sf
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ram_restored:
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/* Restore registers, and return */
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ldmfd sp!, {r4 - r12, pc}
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/* Active SDRAMC self-refresh mode */
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ldr r3, [r2, #AT91_SDRAMC_LPR]
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str r3, .saved_sam9_lpr
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bic r3, r3, #AT91_SDRAMC_LPCB
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orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_SDRAMC_LPR]
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sdramc_exit_sf:
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_SDRAMC_LPR]
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exit_sramc_sf:
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mov pc, lr
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ENDPROC(at91_sramc_self_refresh)
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.pmc_base:
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.word 0
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.sramc_base:
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.word 0
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.sramc1_base:
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.word 0
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.memtype:
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.word 0
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.saved_mckr:
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.word 0
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.saved_pllar:
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.word 0
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.saved_sam9_lpr:
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.word 0
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.saved_sam9_lpr1:
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.word 0
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.saved_sam9_mdr:
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.word 0
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.saved_sam9_mdr1:
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.word 0
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