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drm/nouveau/gr/gf100-: virtualise init_sked_hww_esr

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2018-05-08 20:39:46 +10:00
parent 2b297b0d6d
commit 0a5b97304b
12 changed files with 26 additions and 4 deletions
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4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
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@ -2036,6 +2036,10 @@ gf100_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
if (gr->func->init_sked_hww_esr)
gr->func->init_sked_hww_esr(gr);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -133,6 +133,7 @@ struct gf100_gr_func {
void (*init_fecs_exceptions)(struct gf100_gr *);
void (*init_ds_hww_esr_2)(struct gf100_gr *);
void (*init_40601c)(struct gf100_gr *);
void (*init_sked_hww_esr)(struct gf100_gr *);
void (*init_ppc_exceptions)(struct gf100_gr *);
void (*set_hww_esr_report_mask)(struct gf100_gr *);
const struct gf100_gr_pack *mmio;
@ -163,6 +164,7 @@ int gk104_gr_init(struct gf100_gr *);
void gk104_gr_init_vsc_stream_master(struct gf100_gr *);
void gk104_gr_init_rop_active_fbps(struct gf100_gr *);
void gk104_gr_init_ppc_exceptions(struct gf100_gr *);
void gk104_gr_init_sked_hww_esr(struct gf100_gr *);
int gk20a_gr_init(struct gf100_gr *);

9
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View File

@ -380,6 +380,12 @@ gk104_clkgate_pack[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
void
gk104_gr_init_sked_hww_esr(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000);
}
static void
gk104_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
@ -451,7 +457,7 @@ gk104_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x407020, 0x40000000);
gr->func->init_sked_hww_esr(gr);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@ -527,6 +533,7 @@ gk104_gr = {
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gk104_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk104_gr_pack_mmio,
.fecs.ucode = &gk104_gr_fecs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
View File

@ -343,6 +343,7 @@ gk110_gr = {
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk110_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
View File

@ -109,6 +109,7 @@ gk110b_gr = {
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk110b_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
View File

@ -168,6 +168,7 @@ gk208_gr = {
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk208_gr_pack_mmio,
.fecs.ucode = &gk208_gr_fecs_ucode,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View File

@ -378,7 +378,7 @@ gm107_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x407020, 0x40000000);
gr->func->init_sked_hww_esr(gr);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@ -456,6 +456,7 @@ gm107_gr = {
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_bios_2 = gm107_gr_init_bios_2,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gm107_gr_pack_mmio,
.fecs.ucode = &gm107_gr_fecs_ucode,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View File

@ -106,7 +106,7 @@ gm200_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x407020, 0x40000000);
gr->func->init_sked_hww_esr(gr);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@ -202,6 +202,7 @@ gm200_gr = {
.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 2,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
View File

@ -76,7 +76,7 @@ gp100_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x407020, 0x40000000);
gr->func->init_sked_hww_esr(gr);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@ -134,6 +134,7 @@ gp100_gr = {
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 2,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
View File

@ -51,6 +51,7 @@ gp102_gr = {
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 3,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
View File

@ -37,6 +37,7 @@ gp107_gr = {
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 1,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
View File

@ -35,6 +35,7 @@ gp10b_gr = {
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 1,