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drm/amdgpu: support memory training for sienna_cichlid
Add memory training support for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -532,6 +532,7 @@ static int gddr6_mem_train_support(struct amdgpu_device *adev)
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switch (hw_v) {
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case HW_REV(11, 0, 0):
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case HW_REV(11, 0, 5):
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case HW_REV(11, 0, 7):
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ret = 1;
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break;
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default:
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@ -561,7 +562,8 @@ int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev)
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adev->fw_vram_usage.mem_train_support = false;
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if (adev->asic_type != CHIP_NAVI10 &&
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adev->asic_type != CHIP_NAVI14)
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adev->asic_type != CHIP_NAVI14 &&
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adev->asic_type != CHIP_SIENNA_CICHLID)
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return 0;
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if (amdgpu_sriov_vf(adev))
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