drm/amdgpu: support memory training for sienna_cichlid

Add memory training support for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao 2020-05-21 15:35:46 +08:00 committed by Alex Deucher
parent 83d7f66a53
commit 0a4fa83c2a

View File

@ -532,6 +532,7 @@ static int gddr6_mem_train_support(struct amdgpu_device *adev)
switch (hw_v) {
case HW_REV(11, 0, 0):
case HW_REV(11, 0, 5):
case HW_REV(11, 0, 7):
ret = 1;
break;
default:
@ -561,7 +562,8 @@ int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev)
adev->fw_vram_usage.mem_train_support = false;
if (adev->asic_type != CHIP_NAVI10 &&
adev->asic_type != CHIP_NAVI14)
adev->asic_type != CHIP_NAVI14 &&
adev->asic_type != CHIP_SIENNA_CICHLID)
return 0;
if (amdgpu_sriov_vf(adev))