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Resolve static analysis warnings generated by files in

Browse Source 
arch/arm/mach-omap1, arch/arm/mach-omap2, and arch/arm/plat-omap.
 Fixes all but one sparse warning and most of the useful
 cppcheck warnings (excepting the warnings generated by the
 dmtimer integration code which is going up via 3.4-rc fixes)
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Merge tag 'omap-cleanup-a2-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-sparse

Resolve static analysis warnings generated by files in
arch/arm/mach-omap1, arch/arm/mach-omap2, and arch/arm/plat-omap.
Fixes all but one sparse warning and most of the useful
cppcheck warnings (excepting the warnings generated by the
dmtimer integration code which is going up via 3.4-rc fixes)
This commit is contained in:
Tony Lindgren 2012-04-18 10:09:26 -07:00
commit 09f45b8310
53 changed files with 160 additions and 164 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm/mach-omap1/Makefile
View File

@ -12,6 +12,9 @@ endif
obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
# OCPI interconnect support for 1710, 1610 and 5912
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
# Power Management
obj-$(CONFIG_PM) += pm.o sleep.o
@ -28,13 +31,15 @@ usb-fs-$(CONFIG_USB) := usb.o
obj-y += $(usb-fs-m) $(usb-fs-y)
# Specific board support
obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o
obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o \
board-nand.o
obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o
obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o
obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o board-nand.o
obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o
obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o
obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \
board-nand.o
obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o

2
arch/arm/mach-omap1/ams-delta-fiq.c
View File

@ -102,7 +102,7 @@ void __init ams_delta_init_fiq(void)
}
retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0);
IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
if (retval < 0) {
pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
release_fiq(&fh);

16
arch/arm/mach-omap1/board-fsample.c
View File

@ -185,20 +185,6 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define FSAMPLE_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct mtd_info *mtd)
@ -216,7 +202,7 @@ static struct platform_nand_data nand_data = {
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.cmd_ctrl = omap1_nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};

17
arch/arm/mach-omap1/board-h2.c
View File

@ -179,20 +179,6 @@ static struct mtd_partition h2_nand_partitions[] = {
},
};
static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define H2_NAND_RB_GPIO_PIN 62
static int h2_nand_dev_ready(struct mtd_info *mtd)
@ -212,9 +198,8 @@ static struct platform_nand_data h2_nand_platdata = {
.part_probe_types = h2_part_probes,
},
.ctrl = {
.cmd_ctrl = h2_nand_cmd_ctl,
.cmd_ctrl = omap1_nand_cmd_ctl,
.dev_ready = h2_nand_dev_ready,
},
};

16
arch/arm/mach-omap1/board-h3.c
View File

@ -181,20 +181,6 @@ static struct mtd_partition nand_partitions[] = {
},
};
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define H3_NAND_RB_GPIO_PIN 10
static int nand_dev_ready(struct mtd_info *mtd)
@ -214,7 +200,7 @@ static struct platform_nand_data nand_platdata = {
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.cmd_ctrl = omap1_nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},

37
arch/arm/mach-omap1/board-nand.c Normal file
View File

@ -0,0 +1,37 @@
/*
* linux/arch/arm/mach-omap1/board-nand.c
*
* Common OMAP1 board NAND code
*
* Copyright (C) 2004, 2012 Texas Instruments, Inc.
* Copyright (C) 2002 MontaVista Software, Inc.
* Copyright (C) 2001 RidgeRun, Inc.
* Author: RidgeRun, Inc.
* Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include "common.h"
void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, this->IO_ADDR_W + mask);
}

4
arch/arm/mach-omap1/board-palmz71.c
View File

@ -289,10 +289,10 @@ palmz71_gpio_setup(int early)
gpio_direction_input(PALMZ71_USBDETECT_GPIO);
if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
palmz71_powercable, IRQF_SAMPLE_RANDOM,
"palmz71-cable", 0))
"palmz71-cable", NULL))
printk(KERN_ERR
"IRQ request for power cable failed!\n");
palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), 0);
palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL);
}
}

16
arch/arm/mach-omap1/board-perseus2.c
View File

@ -143,20 +143,6 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct mtd_info *mtd)
@ -174,7 +160,7 @@ static struct platform_nand_data nand_data = {
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.cmd_ctrl = omap1_nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};

3
arch/arm/mach-omap1/clock.c
View File

@ -194,9 +194,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
{
/* Find the highest supported frequency <= rate and switch to it */
struct mpu_rate * ptr;
unsigned long dpll1_rate, ref_rate;
unsigned long ref_rate;
dpll1_rate = ck_dpll1_p->rate;
ref_rate = ck_ref_p->rate;
for (ptr = omap1_rate_table; ptr->rate; ptr++) {

11
arch/arm/mach-omap1/common.h
View File

@ -27,6 +27,7 @@
#define __ARCH_ARM_MACH_OMAP1_COMMON_H
#include <plat/common.h>
#include <linux/mtd/mtd.h>
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
void omap7xx_map_io(void);
@ -56,8 +57,16 @@ void omap1_init_early(void);
void omap1_init_irq(void);
void omap1_restart(char, const char *);
extern void __init omap_check_revision(void);
extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
unsigned int ctrl);
extern struct sys_timer omap1_timer;
extern bool omap_32k_timer_init(void);
extern void __init omap_init_consistent_dma_size(void);
extern u32 omap_irq_flags;
extern int ocpi_enable(void);
#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */

2
arch/arm/mach-omap1/fpga.c
View File

@ -87,7 +87,7 @@ static void fpga_mask_ack_irq(struct irq_data *d)
fpga_ack_irq(d);
}
void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
static void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
{
u32 stat;
int fpga_irq;

2
arch/arm/mach-omap1/id.c
View File

@ -21,6 +21,8 @@
#include <mach/hardware.h>
#include "common.h"
#define OMAP_DIE_ID_0 0xfffe1800
#define OMAP_DIE_ID_1 0xfffe1804
#define OMAP_PRODUCTION_ID_0 0xfffe2000

3
arch/arm/mach-omap1/io.c
View File

@ -18,13 +18,12 @@
#include <plat/mux.h>
#include <plat/tc.h>
#include <plat/dma.h>
#include "iomap.h"
#include "common.h"
#include "clock.h"
extern void omap_check_revision(void);
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.

2
arch/arm/mach-omap1/irq.c
View File

@ -49,6 +49,8 @@
#include <mach/hardware.h>
#include "common.h"
#define IRQ_BANK(irq) ((irq) >> 5)
#define IRQ_BIT(irq) ((irq) & 0x1f)

7
arch/arm/mach-omap1/lcd_dma.c
View File

@ -57,7 +57,7 @@ static struct lcd_dma_info {
void *cb_data;
int active;
unsigned long addr, size;
unsigned long addr;
int rotate, data_type, xres, yres;
int vxres;
int mirror;
@ -77,11 +77,6 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
void omap_set_lcd_dma_src_port(int port)
{
lcd_dma.src_port = port;
}
void omap_set_lcd_dma_ext_controller(int external)
{
lcd_dma.ext_ctrl = external;

7
arch/arm/plat-omap/ocpi.c → arch/arm/mach-omap1/ocpi.c
View File

@ -4,6 +4,7 @@
* Minimal OCP bus support for omap16xx
*
* Copyright (C) 2003 - 2005 Nokia Corporation
* Copyright (C) 2012 Texas Instruments, Inc.
* Written by Tony Lindgren <tony@atomide.com>
*
* Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>.
@ -35,6 +36,8 @@
#include <mach/hardware.h>
#include "common.h"
#define OCPI_BASE 0xfffec320
#define OCPI_FAULT (OCPI_BASE + 0x00)
#define OCPI_CMD_FAULT (OCPI_BASE + 0x04)
@ -64,7 +67,7 @@ int ocpi_enable(void)
/* Enable access for OHCI in OCPI */
val = omap_readl(OCPI_PROT);
val &= ~0xff;
//val &= (1 << 0); /* Allow access only to EMIFS */
/* val &= (1 << 0); Allow access only to EMIFS */
omap_writel(val, OCPI_PROT);
val = omap_readl(OCPI_SEC);
@ -86,7 +89,7 @@ static int __init omap_ocpi_init(void)
clk_enable(ocpi_ck);
ocpi_enable();
printk("OMAP OCPI interconnect driver loaded\n");
pr_info("OMAP OCPI interconnect driver loaded\n");
return 0;
}

9
arch/arm/mach-omap1/pm.c
View File

@ -569,11 +569,10 @@ static int omap_pm_read_proc(
static void omap_pm_init_proc(void)
{
struct proc_dir_entry *entry;
entry = create_proc_read_entry("driver/omap_pm",
S_IWUSR | S_IRUGO, NULL,
omap_pm_read_proc, NULL);
/* XXX Appears to leak memory */
create_proc_read_entry("driver/omap_pm",
S_IWUSR | S_IRUGO, NULL,
omap_pm_read_proc, NULL);
}
#endif /* DEBUG && CONFIG_PROC_FS */

2
arch/arm/mach-omap1/reset.c
View File

@ -8,6 +8,8 @@
#include <mach/hardware.h>
#include "common.h"
void omap1_restart(char mode, const char *cmd)
{
/*

3
arch/arm/mach-omap1/timer.c
View File

@ -54,8 +54,7 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev,
return 0;
}
int __init omap1_dm_timer_init(void)
static int __init omap1_dm_timer_init(void)
{
int i;
int ret;

3
arch/arm/mach-omap1/usb.c
View File

@ -29,6 +29,8 @@
#include <plat/mux.h>
#include <plat/usb.h>
#include "common.h"
/* These routines should handle the standard chip-specific modes
* for usb0/1/2 ports, covering basic mux and transceiver setup.
*
@ -138,6 +140,7 @@ static inline void ohci_device_init(struct omap_usb_config *pdata)
if (cpu_is_omap7xx())
ohci_resources[1].start = INT_7XX_USB_HHC_1;
pdata->ohci_device = &ohci_device;
pdata->ocpi_enable = &ocpi_enable;
}
#else

35
arch/arm/mach-omap2/am35xx-emac.c
View File

@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = {
static void am35xx_enable_emac_int(void)
{
u32 regval;
u32 v;
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
AM35XX_CPGMAC_C0_TX_PULSE_CLR |
AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
AM35XX_CPGMAC_C0_RX_THRESH_CLR);
omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
}
static void am35xx_disable_emac_int(void)
{
u32 regval;
u32 v;
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
AM35XX_CPGMAC_C0_TX_PULSE_CLR);
omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
}
static struct emac_platform_data am35xx_emac_pdata = {
@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = {
void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
{
unsigned int regval;
u32 v;
int err;
am35xx_emac_pdata.rmii_en = rmii_en;
@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
return;
}
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
v &= ~AM35XX_CPGMACSS_SW_RST;
omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
}

8
arch/arm/mach-omap2/board-omap3evm.c
View File

@ -630,13 +630,13 @@ static struct regulator_consumer_supply dummy_supplies[] = {
static void __init omap3_evm_init(void)
{
struct omap_board_mux *obm;
omap3_evm_get_revision();
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
if (cpu_is_omap3630())
omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
else
omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
omap3_mux_init(obm, OMAP_PACKAGE_CBB);
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);

8
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -230,7 +230,7 @@ static struct platform_device omap_vwlan_device = {
},
};
struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
static struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
/* PANDA ref clock is 38.4 MHz */
.board_ref_clock = 2,
};
@ -439,7 +439,7 @@ static struct panel_dvi_platform_data omap4_dvi_panel = {
.i2c_bus_num = 3,
};
struct omap_dss_device omap4_panda_dvi_device = {
static struct omap_dss_device omap4_panda_dvi_device = {
.type = OMAP_DISPLAY_TYPE_DPI,
.name = "dvi",
.driver_name = "dvi",
@ -449,7 +449,7 @@ struct omap_dss_device omap4_panda_dvi_device = {
.channel = OMAP_DSS_CHANNEL_LCD2,
};
int __init omap4_panda_dvi_init(void)
static int __init omap4_panda_dvi_init(void)
{
int r;
@ -510,7 +510,7 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
.default_device = &omap4_panda_dvi_device,
};
void __init omap4_panda_display_init(void)
static void __init omap4_panda_display_init(void)
{
int r;

4
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -872,11 +872,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
.resource_config = twl4030_rconfig,
};
struct twl4030_vibra_data rx51_vibra_data __initdata = {
static struct twl4030_vibra_data rx51_vibra_data __initdata = {
.coexist = 0,
};
struct twl4030_audio_data rx51_audio_data __initdata = {
static struct twl4030_audio_data rx51_audio_data __initdata = {
.audio_mclk = 26000000,
.vibra = &rx51_vibra_data,
};

1
arch/arm/mach-omap2/board-zoom-display.c
View File

@ -16,6 +16,7 @@
#include <linux/spi/spi.h>
#include <plat/mcspi.h>
#include <video/omapdss.h>
#include <mach/board-zoom.h>
#define LCD_PANEL_RESET_GPIO_PROD 96
#define LCD_PANEL_RESET_GPIO_PILOT 55

2
arch/arm/mach-omap2/common.h
View File

@ -134,8 +134,6 @@ void omap4_map_io(void);
void ti81xx_map_io(void);
void omap_barriers_init(void);
extern void __init omap_init_consistent_dma_size(void);
/**
* omap_test_timeout - busy-loop, testing a condition
* @cond: condition to test until it evaluates to true

7
arch/arm/mach-omap2/devices.c
View File

@ -42,7 +42,6 @@
static int __init omap3_l3_init(void)
{
int l;
struct omap_hwmod *oh;
struct platform_device *pdev;
char oh_name[L3_MODULES_MAX_LEN];
@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
if (!(cpu_is_omap34xx()))
return -ENODEV;
l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
oh = omap_hwmod_lookup(oh_name);
@ -72,7 +71,7 @@ postcore_initcall(omap3_l3_init);
static int __init omap4_l3_init(void)
{
int l, i;
int i;
struct omap_hwmod *oh[3];
struct platform_device *pdev;
char oh_name[L3_MODULES_MAX_LEN];
@ -89,7 +88,7 @@ static int __init omap4_l3_init(void)
return -ENODEV;
for (i = 0; i < L3_MODULES; i++) {
l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
oh[i] = omap_hwmod_lookup(oh_name);
if (!(oh[i]))

2
arch/arm/mach-omap2/gpio.c
View File

@ -58,7 +58,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
if (!pdata) {
if (!pdata->regs) {
pr_err("gpio%d: Memory allocation failed\n", id);
return -ENOMEM;
}

3
arch/arm/mach-omap2/gpmc-onenand.c
View File

@ -176,7 +176,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
const int t_wpl = 40;
const int t_wph = 30;
int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
int err, ticks_cez;
int cs = cfg->cs, freq = *freq_ptr;
@ -240,7 +240,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
break;
}
tick_ns = gpmc_ticks_to_ns(1);
div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
gpmc_clk_ns = gpmc_ticks_to_ns(div);
if (gpmc_clk_ns < 15) /* >66Mhz */

3
arch/arm/mach-omap2/gpmc.c
View File

@ -755,8 +755,7 @@ static int __init gpmc_init(void)
irq++;
}
ret = request_irq(gpmc_irq,
gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
if (ret)
pr_err("gpmc: irq-%d could not claim: err %d\n",
gpmc_irq, ret);

2
arch/arm/mach-omap2/hwspinlock.c
View File

@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
.base_id = 0,
};
int __init hwspinlocks_init(void)
static int __init hwspinlocks_init(void)
{
int retval = 0;
struct omap_hwmod *oh;

1
arch/arm/mach-omap2/io.c
View File

@ -31,6 +31,7 @@
#include <plat/omap-pm.h>
#include <plat/omap_hwmod.h>
#include <plat/multi.h>
#include <plat/dma.h>
#include "iomap.h"
#include "voltage.h"

3
arch/arm/mach-omap2/irq.c
View File

@ -25,6 +25,7 @@
#include <mach/hardware.h>
#include "iomap.h"
#include "common.h"
/* selected INTC register offsets */
@ -334,7 +335,7 @@ void omap_intc_restore_context(void)
void omap3_intc_suspend(void)
{
/* A pending interrupt would prevent OMAP from entering suspend */
omap_ack_irq(0);
omap_ack_irq(NULL);
}
void omap3_intc_prepare_idle(void)

2
arch/arm/mach-omap2/mux.c
View File

@ -247,7 +247,7 @@ int __init omap_mux_init_signal(const char *muxname, int val)
int mux_mode;
mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
if (mux_mode < 0)
if (mux_mode < 0 || !mux)
return mux_mode;
old_mode = omap_mux_read(partition, mux->reg_offset);

1
arch/arm/mach-omap2/omap-secure.c
View File

@ -18,6 +18,7 @@
#include <asm/cacheflush.h>
#include <asm/memblock.h>
#include <plat/omap-secure.h>
#include <mach/omap-secure.h>
static phys_addr_t omap_secure_memblock_base;

2
arch/arm/mach-omap2/omap-wakeupgen.c
View File

@ -259,7 +259,7 @@ static void irq_save_context(void)
/*
* Clear WakeupGen SAR backup status.
*/
void irq_sar_clear(void)
static void irq_sar_clear(void)
{
u32 val;
val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);

3
arch/arm/mach-omap2/pm24xx.c
View File

@ -171,8 +171,6 @@ static int omap2_allow_mpu_retention(void)
static void omap2_enter_mpu_retention(void)
{
int only_idle = 0;
/* Putting MPU into the WFI state while a transfer is active
* seems to cause the I2C block to timeout. Why? Good question. */
if (omap2_i2c_active())
@ -195,7 +193,6 @@ static void omap2_enter_mpu_retention(void)
omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
OMAP2_PM_PWSTCTRL);
only_idle = 1;
}
omap2_sram_idle();

10
arch/arm/mach-omap2/pm34xx.c
View File

@ -273,7 +273,7 @@ void omap_sram_idle(void)
int per_next_state = PWRDM_POWER_ON;
int core_next_state = PWRDM_POWER_ON;
int per_going_off;
int core_prev_state, per_prev_state;
int core_prev_state;
u32 sdrc_pwr = 0;
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
@ -375,10 +375,8 @@ void omap_sram_idle(void)
pwrdm_post_transition();
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
if (per_next_state < PWRDM_POWER_ON)
omap2_gpio_resume_after_idle();
}
/* Disable IO-PAD and IO-CHAIN wakeup */
if (omap3_has_io_wakeup() &&
@ -702,7 +700,7 @@ static void __init pm_errata_configure(void)
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
struct clockdomain *neon_clkdm, *mpu_clkdm;
int ret;
if (!cpu_is_omap34xx())
@ -757,8 +755,6 @@ static int __init omap3_pm_init(void)
neon_clkdm = clkdm_lookup("neon_clkdm");
mpu_clkdm = clkdm_lookup("mpu_clkdm");
per_clkdm = clkdm_lookup("per_clkdm");
core_clkdm = clkdm_lookup("core_clkdm");
#ifdef CONFIG_SUSPEND
omap_pm_suspend = omap3_pm_suspend;

4
arch/arm/mach-omap2/prm_common.c
View File

@ -237,7 +237,7 @@ void omap_prcm_irq_complete(void)
*/
int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
{
int nr_regs = irq_setup->nr_regs;
int nr_regs;
u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
int offset, i;
struct irq_chip_generic *gc;
@ -246,6 +246,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
if (!irq_setup)
return -EINVAL;
nr_regs = irq_setup->nr_regs;
if (prcm_irq_setup) {
pr_err("PRCM: already initialized; won't reinitialize\n");
return -EINVAL;

2
arch/arm/mach-omap2/serial.c
View File

@ -243,7 +243,7 @@ static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
#endif
char *cmdline_find_option(char *str)
static char *cmdline_find_option(char *str)
{
extern char *saved_command_line;

2
arch/arm/mach-omap2/usb-tusb6010.c
View File

@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
if (tmp > 4)
return -ERANGE;
if (tmp <= 0)
if (tmp == 0)
tmp = 1;
t.page_burst_access = (fclk_ps * tmp) / 1000;

3
arch/arm/plat-omap/Makefile
View File

@ -9,9 +9,6 @@ obj-m :=
obj-n :=
obj- :=
# OCPI interconnect support for 1710, 1610 and 5912
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
# omap_device support (OMAP2+ only at the moment)
obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
obj-$(CONFIG_ARCH_OMAP3) += omap_device.o

1
arch/arm/plat-omap/common.c
View File

@ -20,6 +20,7 @@
#include <plat/board.h>
#include <plat/vram.h>
#include <plat/dsp.h>
#include <plat/dma.h>
#include <plat/omap-secure.h>

13
arch/arm/plat-omap/dma.c
View File

@ -41,6 +41,15 @@
#include <plat/tc.h>
/*
* MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
* channels that an instance of the SDMA IP block can support. Used
* to size arrays. (The actual maximum on a particular SoC may be less
* than this -- for example, OMAP1 SDMA instances only support 17 logical
* DMA channels.)
*/
#define MAX_LOGICAL_DMA_CH_COUNT 32
#undef DEBUG
#ifndef CONFIG_ARCH_OMAP1
@ -883,7 +892,7 @@ void omap_start_dma(int lch)
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch;
char dma_chan_link_map[dma_lch_count];
char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
dma_chan_link_map[lch] = 1;
/* Set the link register of the first channel */
@ -967,7 +976,7 @@ void omap_stop_dma(int lch)
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch = lch;
char dma_chan_link_map[dma_lch_count];
char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
do {

3
arch/arm/plat-omap/dmtimer.c
View File

@ -349,11 +349,12 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
int omap_dm_timer_stop(struct omap_dm_timer *timer)
{
unsigned long rate = 0;
struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
struct dmtimer_platform_data *pdata;
if (unlikely(!timer))
return -EINVAL;
pdata = timer->pdev->dev.platform_data;
if (!pdata->needs_manual_reset)
rate = clk_get_rate(timer->fclk);

2
arch/arm/plat-omap/include/plat/board.h
View File

@ -91,6 +91,8 @@ struct omap_usb_config {
u32 (*usb0_init)(unsigned nwires, unsigned is_device);
u32 (*usb1_init)(unsigned nwires);
u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
int (*ocpi_enable)(void);
};
struct omap_lcd_config {

2
arch/arm/plat-omap/include/plat/common.h
View File

@ -32,6 +32,8 @@
extern int __init omap_init_clocksource_32k(void);
extern void __init omap_check_revision(void);
extern void omap_reserve(void);
extern int omap_dss_reset(struct omap_hwmod *);

1
arch/arm/plat-omap/include/plat/dma.h
View File

@ -442,6 +442,7 @@ struct omap_system_dma_plat_info {
u32 (*dma_read)(int reg, int lch);
};
extern void __init omap_init_consistent_dma_size(void);
extern void omap_set_dma_priority(int lch, int dst_port, int priority);
extern int omap_request_dma(int dev_id, const char *dev_name,
void (*callback)(int lch, u16 ch_status, void *data),

4
arch/arm/plat-omap/include/plat/dmtimer.h
View File

@ -316,12 +316,12 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
OMAP_TIMER_V1_SYS_STAT_OFFSET;
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
timer->irq_dis = 0;
timer->irq_dis = NULL;
timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
timer->func_base = timer->io_base;
} else {
timer->revision = 2;
timer->sys_stat = 0;
timer->sys_stat = NULL;
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;

2
arch/arm/plat-omap/omap_device.c
View File

@ -475,13 +475,11 @@ static int omap_device_count_resources(struct omap_device *od)
static int omap_device_fill_resources(struct omap_device *od,
struct resource *res)
{
int c = 0;
int i, r;
for (i = 0; i < od->hwmods_cnt; i++) {
r = omap_hwmod_fill_resources(od->hwmods[i], res);
res += r;
c += r;
}
return 0;

4
arch/arm/plat-omap/sram.c
View File

@ -196,8 +196,8 @@ static void __init omap_map_sram(void)
* Looks like we need to preserve some bootloader code at the
* beginning of SRAM for jumping to flash for reboot to work...
*/
memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
omap_sram_size - SRAM_BOOTLOADER_SZ);
memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
omap_sram_size - SRAM_BOOTLOADER_SZ);
}
/*

4
arch/arm/plat-omap/usb.c
View File

@ -31,8 +31,6 @@
#include <mach/hardware.h>
#include "../mach-omap2/common.h"
#ifdef CONFIG_ARCH_OMAP_OTG
void __init
@ -138,8 +136,6 @@ omap_otg_init(struct omap_usb_config *config)
#endif
pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
omap_writel(syscon, OTG_SYSCON_1);
status = 0;
}
#else

5
drivers/usb/host/ohci-omap.c
View File

@ -205,8 +205,9 @@ static int ohci_omap_init(struct usb_hcd *hcd)
need_transceiver = need_transceiver
|| machine_is_omap_h2() || machine_is_omap_h3();
if (cpu_is_omap16xx())
ocpi_enable();
/* XXX OMAP16xx only */
if (config->ocpi_enable)
config->ocpi_enable();
#ifdef CONFIG_USB_OTG
if (need_transceiver) {