mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 15:46:52 +07:00
spi: lpspi: add dma mode support
Add dma mode support for LPSPI. Any frame longer than half txfifosize will be sent by dma mode. For now, there are some limits: 1. The maximum transfer speed in master mode depends on the slave device, at least 40MHz(tested by spi-nor on 8qm-lpddr4-arm2 base board); 2. The maximum transfer speed in slave mode is 15MHz(imx7ulp), 22MHz(8qm/qxp). In order to reach the maximum speed which is mentioned in datasheet, the load of connect wires between master and slave should be less than 15pF. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Acked-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Clark Wang
Mark Brown
parent
c7a4025995
commit
09c04466ce
@ -8,6 +8,8 @@
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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@ -20,6 +22,7 @@
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/platform_data/spi-imx.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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@ -31,6 +34,9 @@
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#define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
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/* The maximum bytes that edma can transfer once.*/
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#define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
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/* i.MX7ULP LPSPI registers */
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#define IMX7ULP_VERID 0x0
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#define IMX7ULP_PARAM 0x4
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@ -64,6 +70,8 @@
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#define IER_FCIE BIT(9)
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#define IER_RDIE BIT(1)
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#define IER_TDIE BIT(0)
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#define DER_RDDE BIT(1)
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#define DER_TDDE BIT(0)
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#define CFGR1_PCSCFG BIT(27)
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#define CFGR1_PINCFG (BIT(24)|BIT(25))
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#define CFGR1_PCSPOL BIT(8)
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@ -91,6 +99,7 @@ struct lpspi_config {
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struct fsl_lpspi_data {
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struct device *dev;
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void __iomem *base;
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unsigned long base_phys;
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struct clk *clk_ipg;
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struct clk *clk_per;
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bool is_slave;
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@ -111,6 +120,11 @@ struct fsl_lpspi_data {
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bool slave_aborted;
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/* DMA */
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bool usedma;
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struct completion dma_rx_completion;
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struct completion dma_tx_completion;
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int chipselect[0];
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};
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@ -158,6 +172,35 @@ static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
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writel(enable, fsl_lpspi->base + IMX7ULP_IER);
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}
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static int fsl_lpspi_bytes_per_word(const int bpw)
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{
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return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
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}
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static bool fsl_lpspi_can_dma(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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unsigned int bytes_per_word;
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if (!controller->dma_rx)
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return false;
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bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
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switch (bytes_per_word)
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{
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case 1:
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case 2:
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case 4:
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break;
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default:
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return false;
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}
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return true;
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}
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static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
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{
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struct fsl_lpspi_data *fsl_lpspi =
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@ -245,11 +288,13 @@ static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
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* For the first transfer, clear TCR_CONTC to assert SS.
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* For subsequent transfer, set TCR_CONTC to keep SS asserted.
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*/
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temp |= TCR_CONT;
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if (fsl_lpspi->is_first_byte)
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temp &= ~TCR_CONTC;
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else
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temp |= TCR_CONTC;
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if (!fsl_lpspi->usedma) {
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temp |= TCR_CONT;
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if (fsl_lpspi->is_first_byte)
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temp &= ~TCR_CONTC;
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else
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temp |= TCR_CONTC;
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}
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}
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writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
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@ -260,7 +305,11 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 temp;
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temp = fsl_lpspi->watermark >> 1 | (fsl_lpspi->watermark >> 1) << 16;
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if (!fsl_lpspi->usedma)
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temp = fsl_lpspi->watermark >> 1 |
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(fsl_lpspi->watermark >> 1) << 16;
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else
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temp = fsl_lpspi->watermark >> 1;
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writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
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@ -302,6 +351,53 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
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return 0;
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}
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static int fsl_lpspi_dma_configure(struct spi_controller *controller)
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{
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int ret;
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enum dma_slave_buswidth buswidth;
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struct dma_slave_config rx = {}, tx = {};
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struct fsl_lpspi_data *fsl_lpspi =
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spi_controller_get_devdata(controller);
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switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
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case 4:
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buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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case 2:
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buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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case 1:
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buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
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break;
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default:
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return -EINVAL;
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}
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tx.direction = DMA_MEM_TO_DEV;
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tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
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tx.dst_addr_width = buswidth;
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tx.dst_maxburst = 1;
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ret = dmaengine_slave_config(controller->dma_tx, &tx);
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if (ret) {
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dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
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ret);
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return ret;
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}
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rx.direction = DMA_DEV_TO_MEM;
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rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
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rx.src_addr_width = buswidth;
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rx.src_maxburst = 1;
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ret = dmaengine_slave_config(controller->dma_rx, &rx);
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if (ret) {
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dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
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ret);
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return ret;
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}
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return 0;
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}
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static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 temp;
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@ -327,10 +423,16 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
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temp |= CR_RRF | CR_RTF | CR_MEN;
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writel(temp, fsl_lpspi->base + IMX7ULP_CR);
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temp = 0;
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if (fsl_lpspi->usedma)
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temp = DER_TDDE | DER_RDDE;
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writel(temp, fsl_lpspi->base + IMX7ULP_DER);
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return 0;
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}
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static int fsl_lpspi_setup_transfer(struct spi_device *spi,
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static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct fsl_lpspi_data *fsl_lpspi =
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@ -363,6 +465,11 @@ static int fsl_lpspi_setup_transfer(struct spi_device *spi,
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else
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fsl_lpspi->watermark = fsl_lpspi->txfifosize;
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if (fsl_lpspi_can_dma(controller, spi, t))
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fsl_lpspi->usedma = 1;
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else
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fsl_lpspi->usedma = 0;
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return fsl_lpspi_config(fsl_lpspi);
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}
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@ -401,8 +508,10 @@ static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 temp;
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/* Disable all interrupt */
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fsl_lpspi_intctrl(fsl_lpspi, 0);
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if (!fsl_lpspi->usedma) {
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/* Disable all interrupt */
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fsl_lpspi_intctrl(fsl_lpspi, 0);
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}
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/* W1C for all flags in SR */
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temp = 0x3F << 8;
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@ -415,6 +524,176 @@ static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
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return 0;
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}
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static void fsl_lpspi_dma_rx_callback(void *cookie)
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{
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struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
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complete(&fsl_lpspi->dma_rx_completion);
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}
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static void fsl_lpspi_dma_tx_callback(void *cookie)
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{
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struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
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complete(&fsl_lpspi->dma_tx_completion);
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}
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static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
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int size)
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{
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unsigned long timeout = 0;
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/* Time with actual data transfer and CS change delay related to HW */
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timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
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/* Add extra second for scheduler related activities */
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timeout += 1;
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/* Double calculated timeout */
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return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
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}
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static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
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struct fsl_lpspi_data *fsl_lpspi,
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struct spi_transfer *transfer)
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{
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struct dma_async_tx_descriptor *desc_tx, *desc_rx;
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unsigned long transfer_timeout;
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unsigned long timeout;
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struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
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int ret;
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ret = fsl_lpspi_dma_configure(controller);
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if (ret)
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return ret;
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desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
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rx->sgl, rx->nents, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc_rx)
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return -EINVAL;
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desc_rx->callback = fsl_lpspi_dma_rx_callback;
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desc_rx->callback_param = (void *)fsl_lpspi;
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dmaengine_submit(desc_rx);
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reinit_completion(&fsl_lpspi->dma_rx_completion);
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dma_async_issue_pending(controller->dma_rx);
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desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
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tx->sgl, tx->nents, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc_tx) {
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dmaengine_terminate_all(controller->dma_tx);
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return -EINVAL;
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}
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desc_tx->callback = fsl_lpspi_dma_tx_callback;
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desc_tx->callback_param = (void *)fsl_lpspi;
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dmaengine_submit(desc_tx);
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reinit_completion(&fsl_lpspi->dma_tx_completion);
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dma_async_issue_pending(controller->dma_tx);
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fsl_lpspi->slave_aborted = false;
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if (!fsl_lpspi->is_slave) {
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transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
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transfer->len);
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/* Wait eDMA to finish the data transfer.*/
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timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
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transfer_timeout);
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if (!timeout) {
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dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
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dmaengine_terminate_all(controller->dma_tx);
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dmaengine_terminate_all(controller->dma_rx);
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fsl_lpspi_reset(fsl_lpspi);
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return -ETIMEDOUT;
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}
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timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
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transfer_timeout);
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if (!timeout) {
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dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
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dmaengine_terminate_all(controller->dma_tx);
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dmaengine_terminate_all(controller->dma_rx);
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fsl_lpspi_reset(fsl_lpspi);
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return -ETIMEDOUT;
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}
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} else {
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if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
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fsl_lpspi->slave_aborted) {
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dev_dbg(fsl_lpspi->dev,
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"I/O Error in DMA TX interrupted\n");
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dmaengine_terminate_all(controller->dma_tx);
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dmaengine_terminate_all(controller->dma_rx);
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fsl_lpspi_reset(fsl_lpspi);
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return -EINTR;
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}
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if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
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fsl_lpspi->slave_aborted) {
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dev_dbg(fsl_lpspi->dev,
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"I/O Error in DMA RX interrupted\n");
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dmaengine_terminate_all(controller->dma_tx);
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dmaengine_terminate_all(controller->dma_rx);
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fsl_lpspi_reset(fsl_lpspi);
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return -EINTR;
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}
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}
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fsl_lpspi_reset(fsl_lpspi);
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return 0;
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}
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static void fsl_lpspi_dma_exit(struct spi_controller *controller)
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{
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if (controller->dma_rx) {
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dma_release_channel(controller->dma_rx);
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controller->dma_rx = NULL;
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}
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if (controller->dma_tx) {
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dma_release_channel(controller->dma_tx);
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controller->dma_tx = NULL;
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}
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}
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static int fsl_lpspi_dma_init(struct device *dev,
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struct fsl_lpspi_data *fsl_lpspi,
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struct spi_controller *controller)
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{
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int ret;
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/* Prepare for TX DMA: */
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controller->dma_tx = dma_request_slave_channel_reason(dev, "tx");
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if (IS_ERR(controller->dma_tx)) {
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ret = PTR_ERR(controller->dma_tx);
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dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
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controller->dma_tx = NULL;
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goto err;
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}
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/* Prepare for RX DMA: */
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controller->dma_rx = dma_request_slave_channel_reason(dev, "rx");
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if (IS_ERR(controller->dma_rx)) {
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ret = PTR_ERR(controller->dma_rx);
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dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
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controller->dma_rx = NULL;
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goto err;
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}
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init_completion(&fsl_lpspi->dma_rx_completion);
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init_completion(&fsl_lpspi->dma_tx_completion);
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controller->can_dma = fsl_lpspi_can_dma;
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controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
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return 0;
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err:
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fsl_lpspi_dma_exit(controller);
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return ret;
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}
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static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
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struct spi_transfer *t)
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{
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@ -449,14 +728,17 @@ static int fsl_lpspi_transfer_one(struct spi_controller *controller,
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int ret;
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fsl_lpspi->is_first_byte = true;
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ret = fsl_lpspi_setup_transfer(spi, t);
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ret = fsl_lpspi_setup_transfer(controller, spi, t);
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if (ret < 0)
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return ret;
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fsl_lpspi_set_cmd(fsl_lpspi);
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fsl_lpspi->is_first_byte = false;
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ret = fsl_lpspi_pio_transfer(controller, t);
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if (fsl_lpspi->usedma)
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ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
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else
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ret = fsl_lpspi_pio_transfer(controller, t);
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if (ret < 0)
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return ret;
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@ -606,6 +888,7 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
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ret = PTR_ERR(fsl_lpspi->base);
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goto out_controller_put;
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}
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fsl_lpspi->base_phys = res->start;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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@ -647,6 +930,13 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
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fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
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fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
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ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
|
||||
if (ret == -EPROBE_DEFER)
|
||||
goto out_controller_put;
|
||||
|
||||
if (ret < 0)
|
||||
dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
|
||||
|
||||
ret = devm_spi_register_controller(&pdev->dev, controller);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "spi_register_controller error.\n");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user