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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-18 17:57:36 +07:00
iommu/qcom: Use accessor functions for iommu private data
Make use of dev_iommu_priv_set/get() functions. Signed-off-by: Joerg Roedel <jroedel@suse.de> Link: https://lore.kernel.org/r/20200326150841.10083-15-joro@8bytes.org
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@ -74,16 +74,19 @@ static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
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static const struct iommu_ops qcom_iommu_ops;
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static struct qcom_iommu_dev * to_iommu(struct iommu_fwspec *fwspec)
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static struct qcom_iommu_dev * to_iommu(struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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if (!fwspec || fwspec->ops != &qcom_iommu_ops)
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return NULL;
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return fwspec->iommu_priv;
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return dev_iommu_priv_get(dev);
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}
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static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid)
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static struct qcom_iommu_ctx * to_ctx(struct device *dev, unsigned asid)
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{
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struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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if (!qcom_iommu)
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return NULL;
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return qcom_iommu->ctxs[asid - 1];
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@ -115,11 +118,14 @@ iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
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static void qcom_iommu_tlb_sync(void *cookie)
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{
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struct iommu_fwspec *fwspec = cookie;
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struct iommu_fwspec *fwspec;
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struct device *dev = cookie;
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unsigned i;
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fwspec = dev_iommu_fwspec_get(dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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unsigned int val, ret;
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iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
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@ -133,11 +139,14 @@ static void qcom_iommu_tlb_sync(void *cookie)
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static void qcom_iommu_tlb_inv_context(void *cookie)
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{
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struct iommu_fwspec *fwspec = cookie;
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struct device *dev = cookie;
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struct iommu_fwspec *fwspec;
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unsigned i;
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fwspec = dev_iommu_fwspec_get(dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
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}
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@ -147,13 +156,16 @@ static void qcom_iommu_tlb_inv_context(void *cookie)
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static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
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size_t granule, bool leaf, void *cookie)
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{
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struct iommu_fwspec *fwspec = cookie;
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struct device *dev = cookie;
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struct iommu_fwspec *fwspec;
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unsigned i, reg;
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reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
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fwspec = dev_iommu_fwspec_get(dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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size_t s = size;
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iova = (iova >> 12) << 12;
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@ -222,9 +234,10 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
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static int qcom_iommu_init_domain(struct iommu_domain *domain,
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struct qcom_iommu_dev *qcom_iommu,
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struct iommu_fwspec *fwspec)
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struct device *dev)
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{
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct io_pgtable_ops *pgtbl_ops;
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struct io_pgtable_cfg pgtbl_cfg;
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int i, ret = 0;
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@ -243,7 +256,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
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};
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qcom_domain->iommu = qcom_iommu;
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pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec);
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pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, dev);
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if (!pgtbl_ops) {
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dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
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ret = -ENOMEM;
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@ -256,7 +269,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
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domain->geometry.force_aperture = true;
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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if (!ctx->secure_init) {
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ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
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@ -363,8 +376,7 @@ static void qcom_iommu_domain_free(struct iommu_domain *domain)
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static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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int ret;
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@ -375,7 +387,7 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev
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/* Ensure that the domain is finalized */
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pm_runtime_get_sync(qcom_iommu->dev);
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ret = qcom_iommu_init_domain(domain, qcom_iommu, fwspec);
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ret = qcom_iommu_init_domain(domain, qcom_iommu, dev);
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pm_runtime_put_sync(qcom_iommu->dev);
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if (ret < 0)
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return ret;
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@ -397,9 +409,9 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev
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static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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unsigned i;
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if (WARN_ON(!qcom_domain->iommu))
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@ -407,7 +419,7 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de
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pm_runtime_get_sync(qcom_iommu->dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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/* Disable the context bank: */
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iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
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@ -514,7 +526,7 @@ static bool qcom_iommu_capable(enum iommu_cap cap)
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static int qcom_iommu_add_device(struct device *dev)
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{
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev_iommu_fwspec_get(dev));
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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struct iommu_group *group;
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struct device_link *link;
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@ -545,7 +557,7 @@ static int qcom_iommu_add_device(struct device *dev)
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static void qcom_iommu_remove_device(struct device *dev)
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{
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev_iommu_fwspec_get(dev));
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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if (!qcom_iommu)
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return;
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@ -557,7 +569,6 @@ static void qcom_iommu_remove_device(struct device *dev)
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static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct qcom_iommu_dev *qcom_iommu;
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struct platform_device *iommu_pdev;
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unsigned asid = args->args[0];
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@ -583,14 +594,14 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
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WARN_ON(asid > qcom_iommu->num_ctxs))
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return -EINVAL;
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if (!fwspec->iommu_priv) {
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fwspec->iommu_priv = qcom_iommu;
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if (!dev_iommu_priv_get(dev)) {
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dev_iommu_priv_set(dev, qcom_iommu);
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} else {
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/* make sure devices iommus dt node isn't referring to
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* multiple different iommu devices. Multiple context
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* banks are ok, but multiple devices are not:
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*/
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if (WARN_ON(qcom_iommu != fwspec->iommu_priv))
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if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev)))
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return -EINVAL;
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}
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