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ARM: SoC platform updates

Browse Source 
SoC updates, mostly refactorings and cleanups of old legacy platforms,
 but also a few more things:
 
 New SoC support this release:
  - NXP/Freescale i.MX7ULP (1x Cortex-A7, Cortex-M4, graphics, etc)
  - Allwinner F1C100, older platform with an ARM926-EJS (ARMv5) core
 
 Cleanups of various platforms:
  - OMAP1 ams-delta does some GPIO cleanups
  - Davinci removes of at24 platform data
  - Samsung cleans up old wakeup, PM debug and secondary core boot code
  - Renesas moves around config options and PM code to drivers/soc for
    sharing with 64-bit and more consistency
  - i.MX, Broadcom and SoCFPGA all have tweaks to lowlevel debug console setups
  - SoCFPGA adds explicit selection of ARM errata and removes some unused code
 
 This tag also contains a few patches that I had queued up as fixes for
 4.20 but didn't send in before the release.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm SoC platform updates from Olof Johansson:
 "SoC updates, mostly refactorings and cleanups of old legacy platforms,
  but also a few more things:

  New SoC support this release:
   - NXP/Freescale i.MX7ULP (1x Cortex-A7, Cortex-M4, graphics, etc)
   - Allwinner F1C100, older platform with an ARM926-EJS (ARMv5) core

  Cleanups of various platforms:
   - OMAP1 ams-delta does some GPIO cleanups
   - Davinci removes of at24 platform data
   - Samsung cleans up old wakeup, PM debug and secondary core boot code
   - Renesas moves around config options and PM code to drivers/soc for
     sharing with 64-bit and more consistency
   - i.MX, Broadcom and SoCFPGA all have tweaks to lowlevel debug
     console setups
   - SoCFPGA adds explicit selection of ARM errata and removes some
     unused code

  This also contains a few patches that I had queued up as fixes for
  4.20 but didn't send in before the release"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (68 commits)
  arm64: dts: renesas: draak: Fix CVBS input
  ARM: omap2: avoid section mismatch warning
  ARM: tegra: avoid section mismatch warning
  ARM: ks8695: fix section mismatch warning
  ARM: pxa: avoid section mismatch warning
  ARM: mmp: fix pxa168_device_usb_phy use on aspenite
  ARM: mmp: fix timer_init calls
  ARM: OMAP1: fix USB configuration for device-only setups
  ARM: OMAP1: add MMC configuration for Palm Tungsten E
  ARM: imx: fix dependencies on imx7ulp
  ARM: meson: select HAVE_ARM_TWD and ARM_GLOBAL_TIMER
  MAINTAINERS: add drivers/soc/amlogic/ to amlogic list
  ARM: imx: add initial support for imx7ulp
  ARM: debug-imx: only define DEBUG_IMX_UART_PORT if needed
  ARM: dts: Fix OMAP4430 SDP Ethernet startup
  ARM: dts: am335x-pdu001: Fix polarity of card detection input
  ARM: OMAP1: ams-delta: Fix audio permanently muted
  ARM: dts: omap5: Fix dual-role mode on Super-Speed port
  arm64: dts: rockchip: fix rk3399-rockpro64 regulator gpios
  ARM: davinci: da850-evm: remove unnecessary include
  ...
This commit is contained in:
Linus Torvalds 2018-12-31 17:27:54 -08:00
commit 0922275ef1
78 changed files with 822 additions and 540 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/sunxi.txt
View File

@ -18,4 +18,5 @@ using one of the following compatible strings:
allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
allwinner,suniv-f1c100s
nextthing,gr8

1
Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
View File

@ -6,6 +6,7 @@ Required properties:
"allwinner,sun4i-a10-wdt"
"allwinner,sun6i-a31-wdt"
"allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
"allwinner,suniv-f1c100s-wdt", "allwinner,sun4i-a10-wdt"
- reg : Specifies base physical address and size of the registers.
Optional properties:

2
MAINTAINERS
View File

@ -1306,7 +1306,6 @@ F: include/dt-bindings/clock/gxbb*
F: Documentation/devicetree/bindings/clock/amlogic*
ARM/Amlogic Meson SoC support
M: Carlo Caione <carlo@caione.org>
M: Kevin Hilman <khilman@baylibre.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-amlogic@lists.infradead.org
@ -1317,6 +1316,7 @@ F: arch/arm/boot/dts/meson*
F: arch/arm64/boot/dts/amlogic/
F: drivers/pinctrl/meson/
F: drivers/mmc/host/meson*
F: drivers/soc/amlogic/
N: meson
ARM/Amlogic Meson SoC Sound Drivers

78
arch/arm/Kconfig.debug
View File

@ -1087,14 +1087,21 @@ choice
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
config DEBUG_SOCFPGA_UART1
config DEBUG_SOCFPGA_ARRIA10_UART1
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART1 for low-level debug"
bool "Use SOCFPGA Arria10 UART1 for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Arria 10) based platforms.
config DEBUG_SOCFPGA_CYCLONE5_UART1
depends on ARCH_SOCFPGA
bool "Use SOCFPGA Cyclone 5 UART1 for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
config DEBUG_SUN9I_UART0
bool "Kernel low-level debugging messages via sun9i UART0"
@ -1192,6 +1199,28 @@ choice
If unsure, say N.
config STM32F4_DEBUG_UART
bool "Use STM32F4 UART for low-level debug"
depends on ARCH_STM32
select DEBUG_STM32_UART
help
Say Y here if you want kernel low-level debugging support
on STM32F4 based platforms, which default UART is wired on
USART1.
If unsure, say N.
config STM32F7_DEBUG_UART
bool "Use STM32F7 UART for low-level debug"
depends on ARCH_STM32
select DEBUG_STM32_UART
help
Say Y here if you want kernel low-level debugging support
on STM32F7 based platforms, which default UART is wired on
USART1.
If unsure, say N.
config TEGRA_DEBUG_UART_AUTO_ODMDATA
bool "Kernel low-level debugging messages via Tegra UART via ODMDATA"
depends on ARCH_TEGRA
@ -1440,21 +1469,21 @@ config DEBUG_OMAP2PLUS_UART
depends on ARCH_OMAP2PLUS
config DEBUG_IMX_UART_PORT
int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
DEBUG_IMX21_IMX27_UART || \
DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART || \
DEBUG_IMX6Q_UART || \
DEBUG_IMX6SL_UART || \
DEBUG_IMX6SX_UART || \
DEBUG_IMX6UL_UART || \
DEBUG_IMX7D_UART
int "i.MX Debug UART Port Selection"
depends on DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
DEBUG_IMX21_IMX27_UART || \
DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART || \
DEBUG_IMX6Q_UART || \
DEBUG_IMX6SL_UART || \
DEBUG_IMX6SX_UART || \
DEBUG_IMX6UL_UART || \
DEBUG_IMX7D_UART
default 1
depends on ARCH_MXC
help
Choose UART port on which kernel low-level debug messages
should be output.
@ -1476,6 +1505,10 @@ config DEBUG_STI_UART
bool
depends on ARCH_STI
config DEBUG_STM32_UART
bool
depends on ARCH_STM32
config DEBUG_SIRFSOC_UART
bool
depends on ARCH_SIRF
@ -1525,6 +1558,7 @@ config DEBUG_LL_INCLUDE
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFSOC_UART
default "debug/sti.S" if DEBUG_STI_UART
default "debug/stm32.S" if DEBUG_STM32_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/ux500.S" if DEBUG_UX500_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT
@ -1655,7 +1689,8 @@ config DEBUG_UART_PHYS
default 0xfe800000 if ARCH_IOP32X
default 0xff690000 if DEBUG_RK32_UART2
default 0xffc02000 if DEBUG_SOCFPGA_UART0
default 0xffc02100 if DEBUG_SOCFPGA_UART1
default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1
default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xffd82340 if ARCH_IOP13XX
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
@ -1762,7 +1797,8 @@ config DEBUG_UART_VIRT
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
default 0xfec02000 if DEBUG_SOCFPGA_UART0
default 0xfec02100 if DEBUG_SOCFPGA_UART1
default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
@ -1811,9 +1847,9 @@ config DEBUG_UART_8250_WORD
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
default y if DEBUG_PICOXCELL_UART || \
DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_UART1 || \
DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \
DEBUG_ALPINE_UART0 || \
DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2

2
arch/arm/boot/dts/am335x-pdu001.dts
View File

@ -585,7 +585,7 @@ &mmc2 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
&sham {

1
arch/arm/boot/dts/omap4-sdp.dts
View File

@ -33,6 +33,7 @@ vdd_eth: fixedregulator-vdd-eth {
gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */
enable-active-high;
regulator-boot-on;
startup-delay-us = <25000>;
};
vbat: fixedregulator-vbat {

1
arch/arm/boot/dts/omap5-board-common.dtsi
View File

@ -701,6 +701,7 @@ &usb3 {
};
&dwc3 {
extcon = <&extcon_usb3>;
dr_mode = "otg";
};

24
arch/arm/include/debug/brcmstb.S
View File

@ -26,8 +26,9 @@
#define UARTA_3390 REG_PHYS_ADDR(0x40a900)
#define UARTA_7250 REG_PHYS_ADDR(0x40b400)
#define UARTA_7260 REG_PHYS_ADDR(0x40c000)
#define UARTA_7268 UARTA_7260
#define UARTA_7255 REG_PHYS_ADDR(0x40c000)
#define UARTA_7260 UARTA_7255
#define UARTA_7268 UARTA_7255
#define UARTA_7271 UARTA_7268
#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
@ -82,15 +83,16 @@ ARM_BE8( rev \rv, \rv )
/* Chip specific detection starts here */
20: checkuart(\rp, \rv, 0x33900000, 3390)
21: checkuart(\rp, \rv, 0x72500000, 7250)
22: checkuart(\rp, \rv, 0x72600000, 7260)
23: checkuart(\rp, \rv, 0x72680000, 7268)
24: checkuart(\rp, \rv, 0x72710000, 7271)
25: checkuart(\rp, \rv, 0x73640000, 7364)
26: checkuart(\rp, \rv, 0x73660000, 7366)
27: checkuart(\rp, \rv, 0x07437100, 74371)
28: checkuart(\rp, \rv, 0x74390000, 7439)
29: checkuart(\rp, \rv, 0x74450000, 7445)
30: checkuart(\rp, \rv, 0x72780000, 7278)
22: checkuart(\rp, \rv, 0x72550000, 7255)
23: checkuart(\rp, \rv, 0x72600000, 7260)
24: checkuart(\rp, \rv, 0x72680000, 7268)
25: checkuart(\rp, \rv, 0x72710000, 7271)
26: checkuart(\rp, \rv, 0x72780000, 7278)
27: checkuart(\rp, \rv, 0x73640000, 7364)
28: checkuart(\rp, \rv, 0x73660000, 7366)
29: checkuart(\rp, \rv, 0x07437100, 74371)
30: checkuart(\rp, \rv, 0x74390000, 7439)
31: checkuart(\rp, \rv, 0x74450000, 7445)
/* No valid UART found */
90: mov \rp, #0

41
arch/arm/include/debug/stm32.S Normal file
View File

@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) STMicroelectronics SA 2017 - All Rights Reserved
* Author: Gerald Baeza <gerald.baeza@st.com> for STMicroelectronics.
*/
#define STM32_UART_BASE 0x40011000 /* USART1 */
#ifdef CONFIG_STM32F4_DEBUG_UART
#define STM32_USART_SR_OFF 0x00
#define STM32_USART_TDR_OFF 0x04
#endif
#ifdef CONFIG_STM32F7_DEBUG_UART
#define STM32_USART_SR_OFF 0x1C
#define STM32_USART_TDR_OFF 0x28
#endif
#define STM32_USART_TC (1 << 6) /* Tx complete */
#define STM32_USART_TXE (1 << 7) /* Tx data reg empty */
.macro addruart, rp, rv, tmp
ldr \rp, =STM32_UART_BASE @ physical base
ldr \rv, =STM32_UART_BASE @ virt base /* NoMMU */
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #STM32_USART_TDR_OFF]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
tst \rd, #STM32_USART_TC @ TC = 1 = tx complete
beq 1001b
.endm

1
arch/arm/mach-bcm/Kconfig
View File

@ -189,6 +189,7 @@ config ARCH_BCM_63XX
bool "Broadcom BCM63xx DSL SoC"
depends on ARCH_MULTI_V7
depends on MMU
select ARCH_HAS_RESET_CONTROLLER
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC

11
arch/arm/mach-bcm/board_bcm2835.c
View File

@ -1,15 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>

10
arch/arm/mach-bcm/platsmp.c
View File

@ -1,15 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014-2015 Broadcom Corporation
* Copyright 2014 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/cpumask.h>

6
arch/arm/mach-bcm/platsmp.h
View File

@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
*/
extern const struct smp_operations bcm2836_smp_ops;

26
arch/arm/mach-davinci/board-da830-evm.c
View File

@ -30,6 +30,7 @@
#include <linux/platform_data/usb-davinci.h>
#include <linux/platform_data/ti-aemif.h>
#include <linux/regulator/machine.h>
#include <linux/nvmem-provider.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -435,6 +436,27 @@ static inline void da830_evm_init_lcdc(int mux_mode)
static inline void da830_evm_init_lcdc(int mux_mode) { }
#endif
static struct nvmem_cell_info da830_evm_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x7f00,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table da830_evm_nvmem_cell_table = {
.nvmem_name = "1-00500",
.cells = da830_evm_nvmem_cells,
.ncells = ARRAY_SIZE(da830_evm_nvmem_cells),
};
static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = {
.nvmem_name = "1-00500",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static struct at24_platform_data da830_evm_i2c_eeprom_info = {
.byte_len = SZ_256K / 8,
.page_size = 64,
@ -620,6 +642,10 @@ static __init void da830_evm_init(void)
__func__, ret);
davinci_serial_init(da8xx_serial_device);
nvmem_add_cell_table(&da830_evm_nvmem_cell_table);
nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1);
i2c_register_board_info(1, da830_evm_i2c_devices,
ARRAY_SIZE(da830_evm_i2c_devices));

30
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -20,7 +20,6 @@
#include <linux/kernel.h>
#include <linux/leds.h>
#include <linux/i2c.h>
#include <linux/platform_data/at24.h>
#include <linux/platform_data/pca953x.h>
#include <linux/input.h>
#include <linux/input/tps6507x-ts.h>
@ -28,6 +27,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/nvmem-provider.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/platform_data/gpio-davinci.h>
@ -100,6 +100,31 @@ static struct mtd_partition da850evm_spiflash_part[] = {
},
};
static struct nvmem_cell_info da850evm_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x0,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table da850evm_nvmem_cell_table = {
/*
* The nvmem name differs from the partition name because of the
* internal works of the nvmem framework.
*/
.nvmem_name = "MAC-Address0",
.cells = da850evm_nvmem_cells,
.ncells = ARRAY_SIZE(da850evm_nvmem_cells),
};
static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = {
.nvmem_name = "MAC-Address0",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static struct flash_platform_data da850evm_spiflash_data = {
.name = "m25p80",
.parts = da850evm_spiflash_part,
@ -1395,6 +1420,9 @@ static __init void da850_evm_init(void)
davinci_serial_init(da8xx_serial_device);
nvmem_add_cell_table(&da850evm_nvmem_cell_table);
nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1);
i2c_register_board_info(1, da850_evm_i2c_devices,
ARRAY_SIZE(da850_evm_i2c_devices));

25
arch/arm/mach-davinci/board-dm365-evm.c
View File

@ -24,6 +24,7 @@
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
#include <linux/mtd/rawnand.h>
#include <linux/nvmem-provider.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
@ -203,6 +204,27 @@ static struct platform_device davinci_aemif_device = {
.num_resources = ARRAY_SIZE(davinci_aemif_resources),
};
static struct nvmem_cell_info davinci_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x7f00,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table davinci_nvmem_cell_table = {
.nvmem_name = "1-00500",
.cells = davinci_nvmem_cells,
.ncells = ARRAY_SIZE(davinci_nvmem_cells),
};
static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
.nvmem_name = "1-00500",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static struct at24_platform_data eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
@ -781,6 +803,9 @@ static __init void dm365_evm_init(void)
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
nvmem_add_cell_table(&davinci_nvmem_cell_table);
nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
evm_init_i2c();
davinci_serial_init(dm365_serial_device);

24
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -22,6 +22,7 @@
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/nvmem-provider.h>
#include <linux/phy.h>
#include <linux/clk.h>
#include <linux/videodev2.h>
@ -510,6 +511,27 @@ static struct pcf857x_platform_data pcf_data_u35 = {
* - ... newer boards may have more
*/
static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x7f00,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
.nvmem_name = "1-00500",
.cells = dm644evm_nvmem_cells,
.ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
};
static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
.nvmem_name = "1-00500",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static struct at24_platform_data eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
@ -842,6 +864,8 @@ static __init void davinci_evm_init(void)
platform_add_devices(davinci_evm_devices,
ARRAY_SIZE(davinci_evm_devices));
#ifdef CONFIG_I2C
nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
evm_init_i2c();
davinci_setup_mmc(0, &dm6446evm_mmc_config);
#endif

24
arch/arm/mach-davinci/board-dm646x-evm.c
View File

@ -32,6 +32,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/nvmem-provider.h>
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/platform_data/gpio-davinci.h>
@ -342,6 +343,27 @@ static struct pcf857x_platform_data pcf_data = {
* - ... newer boards may have more
*/
static struct nvmem_cell_info dm646x_evm_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x7f00,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table dm646x_evm_nvmem_cell_table = {
.nvmem_name = "1-00500",
.cells = dm646x_evm_nvmem_cells,
.ncells = ARRAY_SIZE(dm646x_evm_nvmem_cells),
};
static struct nvmem_cell_lookup dm646x_evm_nvmem_cell_lookup = {
.nvmem_name = "1-00500",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static struct at24_platform_data eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
@ -815,6 +837,8 @@ static __init void evm_init(void)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
#ifdef CONFIG_I2C
nvmem_add_cell_table(&dm646x_evm_nvmem_cell_table);
nvmem_add_cell_lookups(&dm646x_evm_nvmem_cell_lookup, 1);
evm_init_i2c();
#endif

29
arch/arm/mach-davinci/board-mityomapl138.c
View File

@ -15,6 +15,7 @@
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/nvmem-provider.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/platform_data/at24.h>
@ -161,6 +162,31 @@ static void read_factory_config(struct nvmem_device *nvmem, void *context)
mityomapl138_cpufreq_init(partnum);
}
/*
* We don't define a cell for factory config as it will be accessed from the
* board file using the nvmem notifier chain.
*/
static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x64,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
.nvmem_name = "1-00500",
.cells = mityomapl138_nvmem_cells,
.ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
};
static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
.nvmem_name = "1-00500",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static struct at24_platform_data mityomapl138_fd_chip = {
.byte_len = 256,
.page_size = 8,
@ -543,6 +569,9 @@ static void __init mityomapl138_init(void)
davinci_serial_init(da8xx_serial_device);
nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
if (ret)
pr_warn("i2c0 registration failed: %d\n", ret);

2
arch/arm/mach-exynos/common.h
View File

@ -114,8 +114,6 @@ bool __init exynos_secure_firmware_available(void);
void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
extern u32 exynos_get_eint_wake_mask(void);
#ifdef CONFIG_PM_SLEEP
extern void __init exynos_pm_init(void);
#else

26
arch/arm/mach-exynos/platsmp.c
View File

@ -397,38 +397,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
{
int i;
exynos_sysram_init();
exynos_set_delayed_reset_assertion(true);
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_scu_enable();
/*
* Write the address of secondary startup into the
* system-wide flags register. The boot monitor waits
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*
* Try using firmware operation first and fall back to
* boot register if it fails.
*/
for (i = 1; i < max_cpus; ++i) {
unsigned long boot_addr;
u32 mpidr;
u32 core_id;
int ret;
mpidr = cpu_logical_map(i);
core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
boot_addr = __pa_symbol(exynos4_secondary_startup);
ret = exynos_set_boot_addr(core_id, boot_addr);
if (ret)
break;
}
}
#ifdef CONFIG_HOTPLUG_CPU

37
arch/arm/mach-exynos/suspend.c
View File

@ -30,8 +30,6 @@
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <plat/pm-common.h>
#include "common.h"
#define REG_TABLE_END (-1U)
@ -93,6 +91,11 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
{ /* sentinel */ },
};
static u32 exynos_read_eint_wakeup_mask(void)
{
return pmu_raw_readl(EXYNOS_EINT_WAKEUP_MASK);
}
static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
{
const struct exynos_wkup_irq *wkup_irq;
@ -277,8 +280,10 @@ static int exynos5420_cpu_suspend(unsigned long arg)
static void exynos_pm_set_wakeup_mask(void)
{
/* Set wake-up mask registers */
pmu_raw_writel(exynos_get_eint_wake_mask(), EXYNOS_EINT_WAKEUP_MASK);
/*
* Set wake-up mask registers
* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
*/
pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}
@ -488,27 +493,24 @@ static void exynos5420_pm_resume(void)
static int exynos_suspend_enter(suspend_state_t state)
{
u32 eint_wakeup_mask = exynos_read_eint_wakeup_mask();
int ret;
s3c_pm_debug_init();
pr_debug("%s: suspending the system...\n", __func__);
S3C_PMDBG("%s: suspending the system...\n", __func__);
S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
exynos_irqwake_intmask, exynos_get_eint_wake_mask());
pr_debug("%s: wakeup masks: %08x,%08x\n", __func__,
exynos_irqwake_intmask, eint_wakeup_mask);
if (exynos_irqwake_intmask == -1U
&& exynos_get_eint_wake_mask() == -1U) {
&& eint_wakeup_mask == EXYNOS_EINT_WAKEUP_MASK_DISABLED) {
pr_err("%s: No wake-up sources!\n", __func__);
pr_err("%s: Aborting sleep\n", __func__);
return -EINVAL;
}
s3c_pm_save_uarts();
if (pm_data->pm_prepare)
pm_data->pm_prepare();
flush_cache_all();
s3c_pm_check_store();
ret = call_firmware_op(suspend);
if (ret == -ENOSYS)
@ -518,14 +520,11 @@ static int exynos_suspend_enter(suspend_state_t state)
if (pm_data->pm_resume_prepare)
pm_data->pm_resume_prepare();
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
pr_debug("%s: wakeup stat: %08x\n", __func__,
pmu_raw_readl(S5P_WAKEUP_STAT));
s3c_pm_check_restore();
S3C_PMDBG("%s: resuming the system...\n", __func__);
pr_debug("%s: resuming the system...\n", __func__);
return 0;
}
@ -548,8 +547,6 @@ static int exynos_suspend_prepare(void)
return ret;
}
s3c_pm_check_prepare();
return 0;
}
@ -557,8 +554,6 @@ static void exynos_suspend_finish(void)
{
int ret;
s3c_pm_check_cleanup();
ret = regulator_suspend_finish();
if (ret)
pr_warn("Failed to resume regulators from suspend (%d)\n", ret);

9
arch/arm/mach-imx/Kconfig
View File

@ -558,6 +558,15 @@ config SOC_IMX7D
help
This enables support for Freescale i.MX7 Dual processor.
config SOC_IMX7ULP
bool "i.MX7ULP support"
select CLKSRC_IMX_TPM
select PINCTRL_IMX7ULP
select SOC_IMX7D_CA7 if ARCH_MULTI_V7
select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
help
This enables support for Freescale i.MX7 Ultra Low Power processor.
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7

1
arch/arm/mach-imx/Makefile
View File

@ -83,6 +83,7 @@ obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a

1
arch/arm/mach-imx/common.h
View File

@ -120,6 +120,7 @@ void imx6dl_pm_init(void);
void imx6sl_pm_init(void);
void imx6sx_pm_init(void);
void imx6ul_pm_init(void);
void imx7ulp_pm_init(void);
#ifdef CONFIG_PM
void imx51_pm_init(void);

3
arch/arm/mach-imx/cpu.c
View File

@ -145,6 +145,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;
case MXC_CPU_IMX7ULP:
soc_id = "i.MX7ULP";
break;
default:
soc_id = "Unknown";
}

31
arch/arm/mach-imx/mach-imx7ulp.c Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Author: Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "hardware.h"
static void __init imx7ulp_init_machine(void)
{
imx7ulp_pm_init();
mxc_set_cpu_type(MXC_CPU_IMX7ULP);
of_platform_default_populate(NULL, NULL, imx_soc_device_init());
}
static const char *const imx7ulp_dt_compat[] __initconst = {
"fsl,imx7ulp",
NULL,
};
DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
.init_machine = imx7ulp_init_machine,
.dt_compat = imx7ulp_dt_compat,
MACHINE_END

1
arch/arm/mach-imx/mxc.h
View File

@ -44,6 +44,7 @@
#define MXC_CPU_IMX6ULZ 0x6b
#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
#define MXC_CPU_IMX7ULP 0xff
#define IMX_DDR_TYPE_LPDDR2 1

29
arch/arm/mach-imx/pm-imx7ulp.c Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Author: Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#define SMC_PMCTRL 0x10
#define BP_PMCTRL_PSTOPO 16
#define PSTOPO_PSTOP3 0x3
void __init imx7ulp_pm_init(void)
{
struct device_node *np;
void __iomem *smc1_base;
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
smc1_base = of_iomap(np, 0);
WARN_ON(!smc1_base);
/* Partial Stop mode 3 with system/bus clock enabled */
writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO,
smc1_base + SMC_PMCTRL);
iounmap(smc1_base);
}

2
arch/arm/mach-ks8695/board-acs5k.c
View File

@ -100,7 +100,7 @@ static struct i2c_board_info acs5k_i2c_devs[] __initdata = {
},
};
static void acs5k_i2c_init(void)
static void __init acs5k_i2c_init(void)
{
/* The gpio interface */
gpiod_add_lookup_table(&acs5k_i2c_gpiod_table);

2
arch/arm/mach-meson/Kconfig
View File

@ -4,12 +4,14 @@ menuconfig ARCH_MESON
select GPIOLIB
select GENERIC_IRQ_CHIP
select ARM_GIC
select ARM_GLOBAL_TIMER
select CACHE_L2X0
select PINCTRL
select PINCTRL_MESON
select COMMON_CLK
select COMMON_CLK_AMLOGIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
if ARCH_MESON

7
arch/arm/mach-mmp/aspenite.c
View File

@ -29,6 +29,7 @@
#include "addr-map.h"
#include "mfp-pxa168.h"
#include "pxa168.h"
#include "pxa910.h"
#include "irqs.h"
#include "common.h"
@ -256,9 +257,15 @@ static void __init common_init(void)
/* off-chip devices */
platform_device_register(&smc91x_device);
#if IS_ENABLED(CONFIG_USB_SUPPORT)
#if IS_ENABLED(CONFIG_PHY_PXA_USB)
platform_device_register(&pxa168_device_usb_phy);
#endif
#if IS_ENABLED(CONFIG_USB_EHCI_MV)
pxa168_add_usb_host(&pxa168_sph_pdata);
#endif
#endif
}
MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")

2
arch/arm/mach-mmp/common.h
View File

@ -2,7 +2,7 @@
#include <linux/reboot.h>
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
extern void timer_init(int irq);
extern void mmp_timer_init(int irq, unsigned long rate);
extern void __init mmp_map_io(void);
extern void mmp_restart(enum reboot_mode, const char *);

21
arch/arm/mach-mmp/devices.c
View File

@ -240,6 +240,27 @@ void pxa_usb_phy_deinit(void __iomem *phy_reg)
#if IS_ENABLED(CONFIG_USB_SUPPORT)
static u64 __maybe_unused usb_dma_mask = ~(u32)0;
#if IS_ENABLED(CONFIG_PHY_PXA_USB)
struct resource pxa168_usb_phy_resources[] = {
[0] = {
.start = PXA168_U2O_PHYBASE,
.end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa168_device_usb_phy = {
.name = "pxa-usb-phy",
.id = -1,
.resource = pxa168_usb_phy_resources,
.num_resources = ARRAY_SIZE(pxa168_usb_phy_resources),
.dev = {
.dma_mask = &usb_dma_mask,
.coherent_dma_mask = 0xffffffff,
}
};
#endif /* CONFIG_PHY_PXA_USB */
#if IS_ENABLED(CONFIG_USB_MV_UDC)
struct resource pxa168_u2o_resources[] = {
/* regbase */

2
arch/arm/mach-mmp/mmp2-dt.c
View File

@ -26,8 +26,8 @@ static void __init mmp_init_time(void)
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
mmp_dt_init_timer();
of_clk_init(NULL);
mmp_dt_init_timer();
}
static const char *const mmp2_dt_board_compat[] __initconst = {

2
arch/arm/mach-mmp/mmp2.c
View File

@ -134,7 +134,7 @@ void __init mmp2_timer_init(void)
clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
__raw_writel(clk_rst, APBC_TIMERS);
timer_init(IRQ_MMP2_TIMER1);
mmp_timer_init(IRQ_MMP2_TIMER1, 6500000);
}
/* on-chip devices */

2
arch/arm/mach-mmp/pxa168.c
View File

@ -79,7 +79,7 @@ void __init pxa168_timer_init(void)
/* 3.25MHz, bus/functional clock enabled, release reset */
__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
timer_init(IRQ_PXA168_TIMER1);
mmp_timer_init(IRQ_PXA168_TIMER1, 3250000);
}
void pxa168_clear_keypad_wakeup(void)

2
arch/arm/mach-mmp/pxa910.c
View File

@ -116,7 +116,7 @@ void __init pxa910_timer_init(void)
__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
timer_init(IRQ_PXA910_AP1_TIMER1);
mmp_timer_init(IRQ_PXA910_AP1_TIMER1, 3250000);
}
/* on-chip devices */

1
arch/arm/mach-mmp/pxa910.h
View File

@ -22,6 +22,7 @@ extern struct pxa_device_desc pxa910_device_pwm2;
extern struct pxa_device_desc pxa910_device_pwm3;
extern struct pxa_device_desc pxa910_device_pwm4;
extern struct pxa_device_desc pxa910_device_nand;
extern struct platform_device pxa168_device_usb_phy;
extern struct platform_device pxa168_device_u2o;
extern struct platform_device pxa168_device_u2ootg;
extern struct platform_device pxa168_device_u2oehci;

32
arch/arm/mach-mmp/time.c
View File

@ -22,6 +22,7 @@
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
@ -38,12 +39,6 @@
#include "cputype.h"
#include "clock.h"
#ifdef CONFIG_CPU_MMP2
#define MMP_CLOCK_FREQ 6500000
#else
#define MMP_CLOCK_FREQ 3250000
#endif
#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
#define MAX_DELTA (0xfffffffe)
@ -189,19 +184,18 @@ static struct irqaction timer_irq = {
.dev_id = &ckevt,
};
void __init timer_init(int irq)
void __init mmp_timer_init(int irq, unsigned long rate)
{
timer_config();
sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
sched_clock_register(mmp_read_sched_clock, 32, rate);
ckevt.cpumask = cpumask_of(0);
setup_irq(irq, &timer_irq);
clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
MIN_DELTA, MAX_DELTA);
clocksource_register_hz(&cksrc, rate);
clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
}
#ifdef CONFIG_OF
@ -213,7 +207,9 @@ static const struct of_device_id mmp_timer_dt_ids[] = {
void __init mmp_dt_init_timer(void)
{
struct device_node *np;
struct clk *clk;
int irq, ret;
unsigned long rate;
np = of_find_matching_node(NULL, mmp_timer_dt_ids);
if (!np) {
@ -221,6 +217,18 @@ void __init mmp_dt_init_timer(void)
goto out;
}
clk = of_clk_get(np, 0);
if (!IS_ERR(clk)) {
ret = clk_prepare_enable(clk);
if (ret)
goto out;
rate = clk_get_rate(clk) / 2;
} else if (cpu_is_pj4()) {
rate = 6500000;
} else {
rate = 3250000;
}
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
ret = -EINVAL;
@ -231,7 +239,7 @@ void __init mmp_dt_init_timer(void)
ret = -ENOMEM;
goto out;
}
timer_init(irq);
mmp_timer_init(irq, rate);
return;
out:
pr_err("Failed to get timer from device tree with error:%d\n", ret);

6
arch/arm/mach-mmp/ttc_dkb.c
View File

@ -282,6 +282,11 @@ static void __init ttc_dkb_init(void)
sizeof(struct pxa_gpio_platform_data));
platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
#if IS_ENABLED(CONFIG_USB_SUPPORT)
#if IS_ENABLED(CONFIG_PHY_PXA_USB)
platform_device_register(&pxa168_device_usb_phy);
#endif
#if IS_ENABLED(CONFIG_USB_MV_UDC)
pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
platform_device_register(&pxa168_device_u2o);
@ -296,6 +301,7 @@ static void __init ttc_dkb_init(void)
pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
platform_device_register(&pxa168_device_u2ootg);
#endif
#endif
#if IS_ENABLED(CONFIG_MMP_DISP)
add_disp();

2
arch/arm/mach-omap1/Makefile
View File

@ -25,7 +25,7 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
led-y := leds.o
usb-fs-$(CONFIG_USB) := usb.o
usb-fs-$(CONFIG_USB_SUPPORT) := usb.o
obj-y += $(usb-fs-m) $(usb-fs-y)
# Specific board support

2
arch/arm/mach-omap1/ams-delta-fiq-handler.S
View File

@ -18,9 +18,9 @@
#include <linux/platform_data/gpio-omap.h>
#include <asm/assembler.h>
#include <mach/board-ams-delta.h>
#include "ams-delta-fiq.h"
#include "board-ams-delta.h"
#include "iomap.h"
#include "soc.h"

3
arch/arm/mach-omap1/ams-delta-fiq.c
View File

@ -22,11 +22,10 @@
#include <linux/platform_data/ams-delta-fiq.h>
#include <linux/platform_device.h>
#include <mach/board-ams-delta.h>
#include <asm/fiq.h>
#include "ams-delta-fiq.h"
#include "board-ams-delta.h"
static struct fiq_handler fh = {
.name = "ams-delta-fiq"

112
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -36,7 +36,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/board-ams-delta.h>
#include <linux/platform_data/keypad-omap.h>
#include <mach/mux.h>
@ -45,6 +44,7 @@
#include <mach/usb.h>
#include "ams-delta-fiq.h"
#include "board-ams-delta.h"
#include "iomap.h"
#include "common.h"
@ -167,7 +167,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
.pins[0] = 2,
};
#define LATCH1_GPIO_BASE 232
#define LATCH1_NGPIO 8
static struct resource latch1_resources[] = {
@ -183,7 +182,6 @@ static struct resource latch1_resources[] = {
static struct bgpio_pdata latch1_pdata = {
.label = LATCH1_LABEL,
.base = LATCH1_GPIO_BASE,
.ngpio = LATCH1_NGPIO,
};
@ -206,11 +204,13 @@ static struct platform_device latch1_gpio_device = {
#define LATCH1_PIN_DOCKIT1 6
#define LATCH1_PIN_DOCKIT2 7
#define LATCH2_NGPIO 16
static struct resource latch2_resources[] = {
[0] = {
.name = "dat",
.start = LATCH2_PHYS,
.end = LATCH2_PHYS + (AMS_DELTA_LATCH2_NGPIO - 1) / 8,
.end = LATCH2_PHYS + (LATCH2_NGPIO - 1) / 8,
.flags = IORESOURCE_MEM,
},
};
@ -219,8 +219,7 @@ static struct resource latch2_resources[] = {
static struct bgpio_pdata latch2_pdata = {
.label = LATCH2_LABEL,
.base = AMS_DELTA_LATCH2_GPIO_BASE,
.ngpio = AMS_DELTA_LATCH2_NGPIO,
.ngpio = LATCH2_NGPIO,
};
static struct platform_device latch2_gpio_device = {
@ -247,8 +246,8 @@ static struct platform_device latch2_gpio_device = {
#define LATCH2_PIN_SCARD_CMDVCC 11
#define LATCH2_PIN_MODEM_NRESET 12
#define LATCH2_PIN_MODEM_CODEC 13
#define LATCH2_PIN_HOOKFLASH1 14
#define LATCH2_PIN_HOOKFLASH2 15
#define LATCH2_PIN_AUDIO_MUTE 14
#define LATCH2_PIN_HOOKFLASH 15
static struct regulator_consumer_supply modem_nreset_consumers[] = {
REGULATOR_SUPPLY("RESET#", "serial8250.1"),
@ -369,15 +368,9 @@ static struct gpiod_lookup_table ams_delta_lcd_gpio_table = {
},
};
/*
* Dynamically allocated GPIO numbers must be obtained fromm GPIO device
* before they can be put in the gpio_led table. Before that happens,
* initialize the table with invalid GPIO numbers, not 0.
*/
static struct gpio_led gpio_leds[] __initdata = {
[LATCH1_PIN_LED_CAMERA] = {
.name = "camera",
.gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
#ifdef CONFIG_LEDS_TRIGGERS
.default_trigger = "ams_delta_camera",
@ -385,27 +378,22 @@ static struct gpio_led gpio_leds[] __initdata = {
},
[LATCH1_PIN_LED_ADVERT] = {
.name = "advert",
.gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_MAIL] = {
.name = "email",
.gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_HANDSFREE] = {
.name = "handsfree",
.gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_VOICEMAIL] = {
.name = "voicemail",
.gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_VOICE] = {
.name = "voice",
.gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
};
@ -415,6 +403,24 @@ static const struct gpio_led_platform_data leds_pdata __initconst = {
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct gpiod_lookup_table leds_gpio_table = {
.table = {
GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_CAMERA, NULL,
LATCH1_PIN_LED_CAMERA, 0),
GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_ADVERT, NULL,
LATCH1_PIN_LED_ADVERT, 0),
GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_MAIL, NULL,
LATCH1_PIN_LED_MAIL, 0),
GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_HANDSFREE, NULL,
LATCH1_PIN_LED_HANDSFREE, 0),
GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_VOICEMAIL, NULL,
LATCH1_PIN_LED_VOICEMAIL, 0),
GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_VOICE, NULL,
LATCH1_PIN_LED_VOICE, 0),
{ },
},
};
static struct i2c_board_info ams_delta_camera_board_info[] = {
{
I2C_BOARD_INFO("ov6650", 0x60),
@ -586,6 +592,8 @@ static int gpiochip_match_by_label(struct gpio_chip *chip, void *data)
static struct gpiod_hog ams_delta_gpio_hogs[] = {
GPIO_HOG(LATCH2_LABEL, LATCH2_PIN_KEYBRD_DATAOUT, "keybrd_dataout",
GPIO_ACTIVE_HIGH, GPIOD_OUT_LOW),
GPIO_HOG(LATCH2_LABEL, LATCH2_PIN_AUDIO_MUTE, "audio_mute",
GPIO_ACTIVE_HIGH, GPIOD_OUT_LOW),
{},
};
@ -675,6 +683,8 @@ static void __init ams_delta_latch2_init(void)
static void __init ams_delta_init(void)
{
struct platform_device *leds_pdev;
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
@ -738,6 +748,12 @@ static void __init ams_delta_init(void)
gpiod_add_lookup_tables(ams_delta_gpio_tables,
ARRAY_SIZE(ams_delta_gpio_tables));
leds_pdev = gpio_led_register_device(PLATFORM_DEVID_NONE, &leds_pdata);
if (!IS_ERR(leds_pdev)) {
leds_gpio_table.dev_id = dev_name(&leds_pdev->dev);
gpiod_add_lookup_table(&leds_gpio_table);
}
omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
omapfb_set_lcd_config(&ams_delta_lcd_config);
@ -794,64 +810,6 @@ static struct platform_device ams_delta_modem_device = {
},
};
/*
* leds-gpio driver doesn't make use of GPIO lookup tables,
* it has to be provided with GPIO numbers over platform data
* if GPIO descriptor info can't be obtained from device tree.
* We could either define GPIO lookup tables and use them on behalf
* of the leds-gpio device, or we can use GPIO driver level methods
* for identification of GPIO numbers as long as we don't support
* device tree. Let's do the latter.
*/
static void __init ams_delta_led_init(struct gpio_chip *chip)
{
struct gpio_desc *gpiod;
int i;
for (i = LATCH1_PIN_LED_CAMERA; i < LATCH1_PIN_DOCKIT1; i++) {
gpiod = gpiochip_request_own_desc(chip, i, "camera-led", 0);
if (IS_ERR(gpiod)) {
pr_warn("%s: %s GPIO %d request failed (%ld)\n",
__func__, LATCH1_LABEL, i, PTR_ERR(gpiod));
continue;
}
/* Assign GPIO numbers to LED device. */
gpio_leds[i].gpio = desc_to_gpio(gpiod);
gpiochip_free_own_desc(gpiod);
}
gpio_led_register_device(PLATFORM_DEVID_NONE, &leds_pdata);
}
/*
* The purpose of this function is to take care of assignment of GPIO numbers
* to platform devices which depend on GPIO lines provided by Amstrad Delta
* latch1 and/or latch2 GPIO devices but don't use GPIO lookup tables.
* The function may be called as soon as latch1/latch2 GPIO devices are
* initilized. Since basic-mmio-gpio driver is not registered before
* device_initcall, this may happen at erliest during device_initcall_sync.
* Dependent devices shouldn't be registered before that, their
* registration may be performed from within this function or later.
*/
static int __init ams_delta_gpio_init(void)
{
struct gpio_chip *chip;
if (!machine_is_ams_delta())
return -ENODEV;
chip = gpiochip_find(LATCH1_LABEL, gpiochip_match_by_label);
if (!chip)
pr_err("%s: latch1 GPIO chip not found\n", __func__);
else
ams_delta_led_init(chip);
return 0;
}
device_initcall_sync(ams_delta_gpio_init);
static int __init modem_nreset_init(void)
{
int err;

24
arch/arm/mach-omap1/include/mach/board-ams-delta.h → arch/arm/mach-omap1/board-ams-delta.h
View File

@ -1,5 +1,5 @@
/*
* arch/arm/plat-omap/include/mach/board-ams-delta.h
* arch/arm/mach-omap1/board-ams-delta.h
*
* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
*
@ -28,10 +28,6 @@
#if defined (CONFIG_MACH_AMS_DELTA)
#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
@ -41,24 +37,6 @@
#define AMS_DELTA_GPIO_PIN_CONFIG 11
#define AMS_DELTA_GPIO_PIN_NAND_RB 12
#define AMS_DELTA_GPIO_PIN_LCD_VBLEN 240
#define AMS_DELTA_GPIO_PIN_LCD_NDISP 241
#define AMS_DELTA_GPIO_PIN_NAND_NCE 242
#define AMS_DELTA_GPIO_PIN_NAND_NRE 243
#define AMS_DELTA_GPIO_PIN_NAND_NWP 244
#define AMS_DELTA_GPIO_PIN_NAND_NWE 245
#define AMS_DELTA_GPIO_PIN_NAND_ALE 246
#define AMS_DELTA_GPIO_PIN_NAND_CLE 247
#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR 248
#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT 249
#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN 250
#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC 251
#define AMS_DELTA_GPIO_PIN_MODEM_NRESET 252
#define AMS_DELTA_GPIO_PIN_MODEM_CODEC 253
#define AMS_DELTA_LATCH2_GPIO_BASE AMS_DELTA_GPIO_PIN_LCD_VBLEN
#define AMS_DELTA_LATCH2_NGPIO 16
#endif /* CONFIG_MACH_AMS_DELTA */
#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */

29
arch/arm/mach-omap1/board-palmte.c
View File

@ -43,6 +43,7 @@
#include <mach/hardware.h>
#include <mach/usb.h>
#include "mmc.h"
#include "common.h"
#define PALMTE_USBDETECT_GPIO 0
@ -208,6 +209,33 @@ static void __init palmte_misc_gpio_setup(void)
gpio_direction_input(PALMTE_USB_OR_DC_GPIO);
}
#if IS_ENABLED(CONFIG_MMC_OMAP)
static struct omap_mmc_platform_data _palmte_mmc_config = {
.nr_slots = 1,
.slots[0] = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.name = "mmcblk",
},
};
static struct omap_mmc_platform_data *palmte_mmc_config[OMAP15XX_NR_MMC] = {
[0] = &_palmte_mmc_config,
};
static void palmte_mmc_init(void)
{
omap1_init_mmc(palmte_mmc_config, OMAP15XX_NR_MMC);
}
#else /* CONFIG_MMC_OMAP */
static void palmte_mmc_init(void)
{
}
#endif /* CONFIG_MMC_OMAP */
static void __init omap_palmte_init(void)
{
/* mux pins for uarts */
@ -228,6 +256,7 @@ static void __init omap_palmte_init(void)
omap_register_i2c_bus(1, 100, NULL, 0);
omapfb_set_lcd_config(&palmte_lcd_config);
palmte_mmc_init();
}
MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")

14
arch/arm/mach-omap1/clock.c
View File

@ -968,7 +968,7 @@ late_initcall(omap_clk_enable_autoidle_all);
static struct dentry *clk_debugfs_root;
static int clk_dbg_show_summary(struct seq_file *s, void *unused)
static int debug_clock_show(struct seq_file *s, void *unused)
{
struct clk *c;
struct clk *pa;
@ -988,17 +988,7 @@ static int clk_dbg_show_summary(struct seq_file *s, void *unused)
return 0;
}
static int clk_dbg_open(struct inode *inode, struct file *file)
{
return single_open(file, clk_dbg_show_summary, inode->i_private);
}
static const struct file_operations debug_clock_fops = {
.open = clk_dbg_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
DEFINE_SHOW_ATTRIBUTE(debug_clock);
static int clk_debugfs_register_one(struct clk *c)
{

3
arch/arm/mach-omap1/devices.c
View File

@ -244,6 +244,9 @@ struct platform_device omap_spi2 = {
static void omap_init_spi100k(void)
{
if (!cpu_is_omap7xx())
return;
omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff);
if (omap_spi1.dev.platform_data)
platform_device_register(&omap_spi1);

6
arch/arm/mach-omap1/id.c
View File

@ -200,10 +200,10 @@ void __init omap_check_revision(void)
printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type);
}
printk(KERN_INFO "OMAP%04x", omap_revision >> 16);
pr_info("OMAP%04x", omap_revision >> 16);
if ((omap_revision >> 8) & 0xff)
printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff);
printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n",
pr_cont("%x", (omap_revision >> 8) & 0xff);
pr_cont(" revision %i handled as %02xxx id: %08x%08x\n",
die_rev, omap_revision & 0xff, system_serial_low,
system_serial_high);
}

2
arch/arm/mach-omap1/include/mach/usb.h
View File

@ -11,7 +11,7 @@
#include <linux/platform_data/usb-omap1.h>
#if IS_ENABLED(CONFIG_USB)
#if IS_ENABLED(CONFIG_USB_SUPPORT)
void omap1_usb_init(struct omap_usb_config *pdata);
#else
static inline void omap1_usb_init(struct omap_usb_config *pdata)

13
arch/arm/mach-omap1/pm.c
View File

@ -532,18 +532,7 @@ static int omap_pm_debug_show(struct seq_file *m, void *v)
return 0;
}
static int omap_pm_debug_open(struct inode *inode, struct file *file)
{
return single_open(file, omap_pm_debug_show,
&inode->i_private);
}
static const struct file_operations omap_pm_debug_fops = {
.open = omap_pm_debug_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
DEFINE_SHOW_ATTRIBUTE(omap_pm_debug);
static void omap_pm_init_debugfs(void)
{

4
arch/arm/mach-omap2/id.c
View File

@ -199,8 +199,8 @@ void __init omap2xxx_check_revision(void)
pr_info("%s", soc_name);
if ((omap_rev() >> 8) & 0x0f)
pr_info("%s", soc_rev);
pr_info("\n");
pr_cont("%s", soc_rev);
pr_cont("\n");
}
#define OMAP3_SHOW_FEATURE(feat) \

6
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -2413,7 +2413,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
* a stub; implementing this properly requires iclk autoidle usecounting in
* the clock code. No return value.
*/
static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
static void _setup_iclk_autoidle(struct omap_hwmod *oh)
{
struct omap_hwmod_ocp_if *os;
@ -2444,7 +2444,7 @@ static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
* reset. Returns 0 upon success or a negative error code upon
* failure.
*/
static int __init _setup_reset(struct omap_hwmod *oh)
static int _setup_reset(struct omap_hwmod *oh)
{
int r;
@ -2505,7 +2505,7 @@ static int __init _setup_reset(struct omap_hwmod *oh)
*
* No return value.
*/
static void __init _setup_postsetup(struct omap_hwmod *oh)
static void _setup_postsetup(struct omap_hwmod *oh)
{
u8 postsetup_state;

2
arch/arm/mach-omap2/pm33xx-core.c
View File

@ -28,7 +28,7 @@ static struct clockdomain *gfx_l4ls_clkdm;
static void __iomem *scu_base;
static struct omap_hwmod *rtc_oh;
static int __init am43xx_map_scu(void)
static int am43xx_map_scu(void)
{
scu_base = ioremap(scu_a9_get_base(), SZ_256);

1
arch/arm/mach-omap2/timer.c
View File

@ -44,7 +44,6 @@
#include <linux/sched_clock.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
#include "omap_hwmod.h"
#include "omap_device.h"

2
arch/arm/mach-pxa/cm-x300.c
View File

@ -564,7 +564,7 @@ static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = {
.exit = cm_x300_u2d_exit,
};
static void cm_x300_init_u2d(void)
static void __init cm_x300_init_u2d(void)
{
pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
}

2
arch/arm/mach-pxa/littleton.c
View File

@ -182,7 +182,7 @@ static struct pxafb_mach_info littleton_lcd_info = {
.lcd_conn = LCD_COLOR_TFT_16BPP,
};
static void littleton_init_lcd(void)
static void __init littleton_init_lcd(void)
{
pxa_set_fb_info(NULL, &littleton_lcd_info);
}

2
arch/arm/mach-pxa/zeus.c
View File

@ -576,7 +576,7 @@ static struct pxaohci_platform_data zeus_ohci_platform_data = {
.flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
};
static void zeus_register_ohci(void)
static void __init zeus_register_ohci(void)
{
/* Port 2 is shared between host and client interface. */
UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;

1
arch/arm/mach-s5pv210/common.h
View File

@ -10,7 +10,6 @@
#define __ARCH_ARM_MACH_S5PV210_COMMON_H
#ifdef CONFIG_PM_SLEEP
u32 exynos_get_eint_wake_mask(void);
void s5pv210_cpu_resume(void);
void s5pv210_pm_init(void);
#else

16
arch/arm/mach-s5pv210/pm.c
View File

@ -32,6 +32,11 @@ static struct sleep_save s5pv210_core_save[] = {
*/
static u32 s5pv210_irqwake_intmask = 0xffffffff;
static u32 s5pv210_read_eint_wakeup_mask(void)
{
return __raw_readl(S5P_EINT_WAKEUP_MASK);
}
/*
* Suspend helpers.
*/
@ -59,8 +64,10 @@ static void s5pv210_pm_prepare(void)
{
unsigned int tmp;
/* Set wake-up mask registers */
__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
/*
* Set wake-up mask registers
* S5P_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
*/
__raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
/* ensure at least INFORM0 has the resume address */
@ -89,6 +96,7 @@ static void s5pv210_pm_prepare(void)
*/
static int s5pv210_suspend_enter(suspend_state_t state)
{
u32 eint_wakeup_mask = s5pv210_read_eint_wakeup_mask();
int ret;
s3c_pm_debug_init();
@ -96,10 +104,10 @@ static int s5pv210_suspend_enter(suspend_state_t state)
S3C_PMDBG("%s: suspending the system...\n", __func__);
S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
s5pv210_irqwake_intmask, exynos_get_eint_wake_mask());
s5pv210_irqwake_intmask, eint_wakeup_mask);
if (s5pv210_irqwake_intmask == -1U
&& exynos_get_eint_wake_mask() == -1U) {
&& eint_wakeup_mask == -1U) {
pr_err("%s: No wake-up sources!\n", __func__);
pr_err("%s: Aborting sleep\n", __func__);
return -EINVAL;

129
arch/arm/mach-shmobile/Kconfig
View File

@ -1,139 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
config PM_RMOBILE
bool
select PM
select PM_GENERIC_DOMAINS
config ARCH_RCAR_GEN1
bool
select PM
select PM_GENERIC_DOMAINS
select RENESAS_INTC_IRQPIN
select SYS_SUPPORTS_SH_TMU
config ARCH_RCAR_GEN2
bool
select HAVE_ARM_ARCH_TIMER
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
select SYS_SUPPORTS_SH_CMT
config ARCH_RMOBILE
bool
select PM_RMOBILE
select SYS_SUPPORTS_SH_CMT
select SYS_SUPPORTS_SH_TMU
menuconfig ARCH_RENESAS
bool "Renesas ARM SoCs"
depends on ARCH_MULTI_V7 && MMU
select ARM_GIC
select GPIOLIB
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select NO_IOPORT_MAP
select PINCTRL
select SOC_BUS
select ZONE_DMA if ARM_LPAE
if ARCH_RENESAS
#comment "Renesas ARM SoCs System Type"
config ARCH_EMEV2
bool "Emma Mobile EV2"
select SYS_SUPPORTS_EM_STI
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select PM
select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_MTU2
select RENESAS_OSTM
config ARCH_R7S9210
bool "RZ/A2 (R7S9210)"
select PM
select PM_GENERIC_DOMAINS
select RENESAS_OSTM
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
select ARCH_RMOBILE
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select RENESAS_IRQC
config ARCH_R8A7740
bool "R-Mobile A1 (R8A77400)"
select ARCH_RMOBILE
select RENESAS_INTC_IRQPIN
config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
config ARCH_R8A7744
bool "RZ/G1N (R8A77440)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
config ARCH_R8A7745
bool "RZ/G1E (R8A77450)"
select ARCH_RCAR_GEN2
config ARCH_R8A77470
bool "RZ/G1C (R8A77470)"
select ARCH_RCAR_GEN2
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select ARCH_RCAR_GEN1
config ARCH_R8A7779
bool "R-Car H1 (R8A77790)"
select ARCH_RCAR_GEN1
config ARCH_R8A7790
bool "R-Car H2 (R8A77900)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select I2C
config ARCH_R8A7791
bool "R-Car M2-W (R8A77910)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select I2C
config ARCH_R8A7792
bool "R-Car V2H (R8A77920)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
config ARCH_R8A7793
bool "R-Car M2-N (R8A7793)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select I2C
config ARCH_R8A7794
bool "R-Car E2 (R8A77940)"
select ARCH_RCAR_GEN2
config ARCH_R9A06G032
bool "RZ/N1D (R9A06G032)"
select ARCH_RZN1
config ARCH_RZN1
bool "RZ/N1 (R9A06G0xx) Family"
select ARM_AMBA
select CPU_V7
config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
select RENESAS_INTC_IRQPIN
endif

1
arch/arm/mach-shmobile/Makefile
View File

@ -35,7 +35,6 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
# PM objects
obj-$(CONFIG_SUSPEND) += suspend.o
obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
# Framework support

22
arch/arm/mach-shmobile/pm-rmobile.h
View File

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*/
#ifndef PM_RMOBILE_H
#define PM_RMOBILE_H
#include <linux/pm_domain.h>
struct rmobile_pm_domain {
struct generic_pm_domain genpd;
struct dev_power_governor *gov;
int (*suspend)(void);
void (*resume)(void);
void __iomem *base;
unsigned int bit_shift;
bool no_debug;
};
#endif /* PM_RMOBILE_H */

1
arch/arm/mach-shmobile/smp-sh73a0.c
View File

@ -12,7 +12,6 @@
#include <linux/delay.h>
#include <asm/smp_plat.h>
#include <asm/smp_twd.h>
#include "common.h"
#include "sh73a0.h"

7
arch/arm/mach-socfpga/Kconfig
View File

@ -11,6 +11,13 @@ menuconfig ARCH_SOCFPGA
select HAVE_ARM_TWD if SMP
select MFD_SYSCON
select PCI_DOMAINS_GENERIC if PCI
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
select PL310_ERRATA_588369
select PL310_ERRATA_727915
select PL310_ERRATA_753970 if PL310
select PL310_ERRATA_769419
if ARCH_SOCFPGA
config SOCFPGA_SUSPEND

2
arch/arm/mach-socfpga/core.h
View File

@ -34,8 +34,6 @@
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
extern void socfpga_init_clocks(void);
extern void socfpga_sysmgr_init(void);
void socfpga_init_l2_ecc(void);
void socfpga_init_ocram_ecc(void);
void socfpga_init_arria10_l2_ecc(void);

2
arch/arm/mach-socfpga/socfpga.c
View File

@ -32,7 +32,7 @@ void __iomem *rst_manager_base_addr;
void __iomem *sdr_ctl_base_addr;
unsigned long socfpga_cpu1start_addr;
void __init socfpga_sysmgr_init(void)
static void __init socfpga_sysmgr_init(void)
{
struct device_node *np;

19
arch/arm/mach-sunxi/Kconfig
View File

@ -1,6 +1,6 @@
menuconfig ARCH_SUNXI
bool "Allwinner SoCs"
depends on ARCH_MULTI_V7
depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
@ -9,9 +9,13 @@ menuconfig ARCH_SUNXI
select PM_OPP
select SUN4I_TIMER
select RESET_CONTROLLER
help
Support for Allwinner ARM-based family of processors
if ARCH_SUNXI
if ARCH_MULTI_V7
config MACH_SUN4I
bool "Allwinner A10 (sun4i) SoCs support"
default ARCH_SUNXI
@ -56,3 +60,16 @@ config ARCH_SUNXI_MC_SMP
select ARM_CPU_SUSPEND
endif
if ARCH_MULTI_V5
config MACH_SUNIV
bool "Allwinner ARMv5 F-series (suniv) SoCs support"
default ARCH_SUNXI
help
Support for Allwinner suniv ARMv5 SoCs.
(F1C100A, F1C100s, F1C200s, F1C500, F1C600)
endif
endif

9
arch/arm/mach-sunxi/sunxi.c
View File

@ -101,3 +101,12 @@ static const char * const sun9i_board_dt_compat[] = {
DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family")
.dt_compat = sun9i_board_dt_compat,
MACHINE_END
static const char * const suniv_board_dt_compat[] = {
"allwinner,suniv-f1c100s",
NULL,
};
DT_MACHINE_START(SUNIV_DT, "Allwinner suniv Family")
.dt_compat = suniv_board_dt_compat,
MACHINE_END

4
arch/arm/mach-tegra/irq.c
View File

@ -72,7 +72,7 @@ static const struct of_device_id tegra114_dt_gic_match[] __initconst = {
{ }
};
static void tegra114_gic_cpu_pm_registration(void)
static void __init tegra114_gic_cpu_pm_registration(void)
{
struct device_node *dn;
@ -85,7 +85,7 @@ static void tegra114_gic_cpu_pm_registration(void)
cpu_pm_register_notifier(&tegra_gic_notifier_block);
}
#else
static void tegra114_gic_cpu_pm_registration(void) { }
static void __init tegra114_gic_cpu_pm_registration(void) { }
#endif
static const struct of_device_id tegra_ictlr_match[] __initconst = {

1
arch/arm/plat-samsung/Kconfig
View File

@ -239,6 +239,7 @@ comment "Power management"
config SAMSUNG_PM_DEBUG
bool "Samsung PM Suspend debug"
depends on PM && DEBUG_KERNEL
depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART
help
Say Y here if you want verbose debugging from the PM Suspend and

60
arch/arm64/Kconfig.platforms
View File

@ -157,70 +157,12 @@ config ARCH_REALTEK
config ARCH_RENESAS
bool "Renesas SoC Platforms"
select GPIOLIB
select PINCTRL
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
select SOC_BUS
select SYS_SUPPORTS_SH_CMT
select SYS_SUPPORTS_SH_TMU
help
This enables support for the ARMv8 based Renesas SoCs.
config ARCH_R8A774A1
bool "Renesas RZ/G2M SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas RZ/G2M SoC.
config ARCH_R8A774C0
bool "Renesas RZ/G2E SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas RZ/G2E SoC.
config ARCH_R8A7795
bool "Renesas R-Car H3 SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car H3 SoC.
config ARCH_R8A7796
bool "Renesas R-Car M3-W SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car M3-W SoC.
config ARCH_R8A77965
bool "Renesas R-Car M3-N SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car M3-N SoC.
config ARCH_R8A77970
bool "Renesas R-Car V3M SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car V3M SoC.
config ARCH_R8A77980
bool "Renesas R-Car V3H SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car V3H SoC.
config ARCH_R8A77990
bool "Renesas R-Car E3 SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car E3 SoC.
config ARCH_R8A77995
bool "Renesas R-Car D3 SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car D3 SoC.
config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER

2
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
View File

@ -195,7 +195,7 @@ composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
port {
ports {
#address-cells = <1>;
#size-cells = <0>;

20
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
View File

@ -97,7 +97,7 @@ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
@ -293,12 +293,12 @@ regulator-state-mem {
};
};
vcc2v8_dvp: LDO_REG2 {
regulator-name = "vcc2v8_dvp";
vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@ -397,7 +397,9 @@ regulator-state-mem {
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <0>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_gpio>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@ -415,6 +417,8 @@ vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_gpio>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@ -519,7 +523,7 @@ lcd_panel_reset: lcd-panel-reset {
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -529,7 +533,7 @@ pmic_int_l: pmic-int-l {
};
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {

241
drivers/soc/renesas/Kconfig
View File

@ -3,30 +3,226 @@ config SOC_RENESAS
bool "Renesas SoC driver support" if COMPILE_TEST && !ARCH_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
ARCH_R8A774A1 || ARCH_R8A774C0 || ARCH_R8A7795 || \
ARCH_R8A7796 || ARCH_R8A77965 || ARCH_R8A77970 || \
ARCH_R8A77980 || ARCH_R8A77990 || ARCH_R8A77995
select SYSC_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
select SYSC_R8A774A1 if ARCH_R8A774A1
select SYSC_R8A774C0 if ARCH_R8A774C0
select SYSC_R8A7779 if ARCH_R8A7779
select SYSC_R8A7790 if ARCH_R8A7790
select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
select SYSC_R8A7792 if ARCH_R8A7792
select SYSC_R8A7794 if ARCH_R8A7794
select SYSC_R8A7795 if ARCH_R8A7795
select SYSC_R8A7796 if ARCH_R8A7796
select SYSC_R8A77965 if ARCH_R8A77965
select SYSC_R8A77970 if ARCH_R8A77970
select SYSC_R8A77980 if ARCH_R8A77980
select SYSC_R8A77990 if ARCH_R8A77990
select SYSC_R8A77995 if ARCH_R8A77995
if SOC_RENESAS
config ARCH_RCAR_GEN1
bool
select PM
select PM_GENERIC_DOMAINS
select RENESAS_INTC_IRQPIN
select RST_RCAR
select SYS_SUPPORTS_SH_TMU
config ARCH_RCAR_GEN2
bool
select HAVE_ARM_ARCH_TIMER
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
select RST_RCAR
select SYS_SUPPORTS_SH_CMT
config ARCH_RCAR_GEN3
bool
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
select RST_RCAR
select SYS_SUPPORTS_SH_CMT
select SYS_SUPPORTS_SH_TMU
config ARCH_RMOBILE
bool
select PM
select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_CMT
select SYS_SUPPORTS_SH_TMU
select SYSC_RMOBILE
config ARCH_RZN1
bool
select ARM_AMBA
if ARM
#comment "Renesas ARM SoCs System Type"
config ARCH_EMEV2
bool "Emma Mobile EV2"
select HAVE_ARM_SCU if SMP
select SYS_SUPPORTS_EM_STI
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select PM
select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_MTU2
select RENESAS_OSTM
config ARCH_R7S9210
bool "RZ/A2 (R7S9210)"
select PM
select PM_GENERIC_DOMAINS
select RENESAS_OSTM
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
select ARCH_RMOBILE
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select RENESAS_IRQC
config ARCH_R8A7740
bool "R-Mobile A1 (R8A77400)"
select ARCH_RMOBILE
select RENESAS_INTC_IRQPIN
config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select SYSC_R8A7743
config ARCH_R8A7744
bool "RZ/G1N (R8A77440)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select SYSC_R8A7743
config ARCH_R8A7745
bool "RZ/G1E (R8A77450)"
select ARCH_RCAR_GEN2
select SYSC_R8A7745
config ARCH_R8A77470
bool "RZ/G1C (R8A77470)"
select ARCH_RCAR_GEN2
select SYSC_R8A77470
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select ARCH_RCAR_GEN1
config ARCH_R8A7779
bool "R-Car H1 (R8A77790)"
select ARCH_RCAR_GEN1
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select SYSC_R8A7779
config ARCH_R8A7790
bool "R-Car H2 (R8A77900)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select I2C
select SYSC_R8A7790
config ARCH_R8A7791
bool "R-Car M2-W (R8A77910)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select I2C
select SYSC_R8A7791
config ARCH_R8A7792
bool "R-Car V2H (R8A77920)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select SYSC_R8A7792
config ARCH_R8A7793
bool "R-Car M2-N (R8A7793)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
select I2C
select SYSC_R8A7791
config ARCH_R8A7794
bool "R-Car E2 (R8A77940)"
select ARCH_RCAR_GEN2
select SYSC_R8A7794
config ARCH_R9A06G032
bool "RZ/N1D (R9A06G032)"
select ARCH_RZN1
config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select RENESAS_INTC_IRQPIN
endif # ARM
if ARM64
config ARCH_R8A774A1
bool "Renesas RZ/G2M SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A774A1
help
This enables support for the Renesas RZ/G2M SoC.
config ARCH_R8A774C0
bool "Renesas RZ/G2E SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A774C0
help
This enables support for the Renesas RZ/G2E SoC.
config ARCH_R8A7795
bool "Renesas R-Car H3 SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A7795
help
This enables support for the Renesas R-Car H3 SoC.
config ARCH_R8A7796
bool "Renesas R-Car M3-W SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A7796
help
This enables support for the Renesas R-Car M3-W SoC.
config ARCH_R8A77965
bool "Renesas R-Car M3-N SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A77965
help
This enables support for the Renesas R-Car M3-N SoC.
config ARCH_R8A77970
bool "Renesas R-Car V3M SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A77970
help
This enables support for the Renesas R-Car V3M SoC.
config ARCH_R8A77980
bool "Renesas R-Car V3H SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A77980
help
This enables support for the Renesas R-Car V3H SoC.
config ARCH_R8A77990
bool "Renesas R-Car E3 SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A77990
help
This enables support for the Renesas R-Car E3 SoC.
config ARCH_R8A77995
bool "Renesas R-Car D3 SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A77995
help
This enables support for the Renesas R-Car D3 SoC.
endif # ARM64
# SoC
config SYSC_R8A7743
bool "RZ/G1M System Controller support" if COMPILE_TEST
@ -103,4 +299,7 @@ config RST_RCAR
config SYSC_RCAR
bool "R-Car System Controller support" if COMPILE_TEST
config SYSC_RMOBILE
bool "R-Mobile System Controller support" if COMPILE_TEST
endif # SOC_RENESAS

1
drivers/soc/renesas/Makefile
View File

@ -27,3 +27,4 @@ endif
# Family
obj-$(CONFIG_RST_RCAR) += rcar-rst.o
obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o
obj-$(CONFIG_SYSC_RMOBILE) += rmobile-sysc.o

37
arch/arm/mach-shmobile/pm-rmobile.c → drivers/soc/renesas/rmobile-sysc.c
View File

@ -18,12 +18,11 @@
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <asm/io.h>
#include "pm-rmobile.h"
/* SYSC */
#define SPDCR 0x08 /* SYS Power Down Control Register */
#define SWUCR 0x14 /* SYS Wakeup Control Register */
@ -32,6 +31,14 @@
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10
struct rmobile_pm_domain {
struct generic_pm_domain genpd;
struct dev_power_governor *gov;
int (*suspend)(void);
void __iomem *base;
unsigned int bit_shift;
};
static inline
struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
{
@ -65,16 +72,13 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
}
}
if (!rmobile_pd->no_debug)
pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
genpd->name, mask,
__raw_readl(rmobile_pd->base + PSTR));
pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask,
__raw_readl(rmobile_pd->base + PSTR));
return 0;
}
static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
bool do_resume)
static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd)
{
unsigned int mask;
unsigned int retry_count;
@ -85,7 +89,7 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
mask = BIT(rmobile_pd->bit_shift);
if (__raw_readl(rmobile_pd->base + PSTR) & mask)
goto out;
return ret;
__raw_writel(mask, rmobile_pd->base + SWUCR);
@ -100,21 +104,16 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
if (!retry_count)
ret = -EIO;
if (!rmobile_pd->no_debug)
pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
rmobile_pd->genpd.name, mask,
__raw_readl(rmobile_pd->base + PSTR));
out:
if (ret == 0 && rmobile_pd->resume && do_resume)
rmobile_pd->resume();
pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
rmobile_pd->genpd.name, mask,
__raw_readl(rmobile_pd->base + PSTR));
return ret;
}
static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
{
return __rmobile_pd_power_up(to_rmobile_pd(genpd), true);
return __rmobile_pd_power_up(to_rmobile_pd(genpd));
}
static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
@ -127,7 +126,7 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
genpd->power_on = rmobile_pd_power_up;
genpd->attach_dev = cpg_mstp_attach_dev;
genpd->detach_dev = cpg_mstp_detach_dev;
__rmobile_pd_power_up(rmobile_pd, false);
__rmobile_pd_power_up(rmobile_pd);
pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
}