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ARM64: DT: Hisilicon SoC DT updates for 4.12

Browse Source 
- Reset the hi6220 mmc hosts to avoid hang
 - Add the binding for the hi3798cv200 SoC and the poplar board
 - Add basic dts files to support the hi3798cv200 poplar board
 - Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
 - Add driver strength MACRO for the hi3660 SoC
 - Add the pinctrl dtsi file for hikey960 board to configure the pins
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Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi into next/dt64

ARM64: DT: Hisilicon SoC DT updates for 4.12

- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins

* tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
  arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
  arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
  dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
  arm64: dts: hi6220: Reset the mmc hosts

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-04-19 06:33:20 -07:00
commit 08fd8c9567
10 changed files with 1507 additions and 0 deletions
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8
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -4,6 +4,14 @@ Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";
Hi3798cv200 Poplar Board
Required root node properties:
- compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";

1
arch/arm64/boot/dts/hisilicon/Makefile
View File

@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb

1
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
View File

@ -8,6 +8,7 @@
/dts-v1/;
#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"
/ {
model = "HiKey960";

162
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts Normal file
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@ -0,0 +1,162 @@
/*
* DTS File for HiSilicon Poplar Development Board
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "hi3798cv200.dtsi"
/ {
model = "HiSilicon Poplar Development Board";
compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
aliases {
serial0 = &uart0;
serial2 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
leds {
compatible = "gpio-leds";
user-led0 {
label = "USER-LED0";
gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
user-led1 {
label = "USER-LED1";
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
default-state = "off";
};
user-led2 {
label = "USER-LED2";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
default-state = "off";
};
user-led3 {
label = "USER-LED3";
gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "cpu0";
default-state = "off";
};
};
};
&gmac1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&eth_phy1>;
phy-mode = "rgmii";
hisilicon,phy-reset-delays-us = <10000 10000 30000>;
eth_phy1: phy@3 {
reg = <3>;
};
};
&gpio1 {
status = "okay";
gpio-line-names = "LS-GPIO-E", "",
"", "",
"", "LS-GPIO-F",
"", "LS-GPIO-J";
};
&gpio2 {
status = "okay";
gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
"LS-GPIO-L", "LS-GPIO-G",
"LS-GPIO-K", "",
"", "";
};
&gpio3 {
status = "okay";
gpio-line-names = "", "",
"", "",
"LS-GPIO-C", "",
"", "LS-GPIO-B";
};
&gpio4 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "LS-GPIO-D",
"", "";
};
&gpio5 {
status = "okay";
gpio-line-names = "", "USER-LED-1",
"USER-LED-2", "",
"", "LS-GPIO-A",
"", "";
};
&gpio6 {
status = "okay";
gpio-line-names = "", "",
"", "USER-LED-0",
"", "",
"", "";
};
&gpio10 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "",
"USER-LED-3", "";
};
&i2c0 {
status = "okay";
label = "LS-I2C0";
};
&i2c2 {
status = "okay";
label = "LS-I2C1";
};
&ir {
status = "okay";
};
&spi0 {
status = "okay";
label = "LS-SPI0";
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
label = "LS-UART0";
};
/* No optional LS-UART1 on Low Speed Expansion Connector. */

411
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi Normal file
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@ -0,0 +1,411 @@
/*
* DTS File for HiSilicon Hi3798cv200 SoC.
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "hisilicon,hi3798cv200";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x100>; /* GICC */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc@f0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
reg = <0x8a22000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
gmacphyrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits =
<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>,
<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>;
};
};
sysctrl: system-controller@8000000 {
compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
reg = <0x8000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
uart0: serial@8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: serial@8b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b02000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_UART2_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
i2c0: i2c@8b10000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b10000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C0_CLK>;
status = "disabled";
};
i2c1: i2c@8b11000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b11000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C1_CLK>;
status = "disabled";
};
i2c2: i2c@8b12000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b12000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C2_CLK>;
status = "disabled";
};
i2c3: i2c@8b13000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b13000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C3_CLK>;
status = "disabled";
};
i2c4: i2c@8b14000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b14000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C4_CLK>;
status = "disabled";
};
spi0: spi@8b1a000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x8b1a000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <1>;
cs-gpios = <&gpio7 1 0>;
clocks = <&crg HISTB_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
emmc: mmc@9830000 {
compatible = "snps,dw-mshc";
reg = <0x9830000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_MMC_CIU_CLK>,
<&crg HISTB_MMC_BIU_CLK>;
clock-names = "ciu", "biu";
};
gpio0: gpio@8b20000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b20000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio1: gpio@8b21000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b21000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio2: gpio@8b22000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b22000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio3: gpio@8b23000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b23000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio4: gpio@8b24000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b24000 0x1000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio5: gpio@8004000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8004000 0x1000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio6: gpio@8b26000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b26000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio7: gpio@8b27000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b27000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio8: gpio@8b28000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b28000 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio9: gpio@8b29000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b29000 0x1000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio10: gpio@8b2a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2a000 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio11: gpio@8b2b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2b000 0x1000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio12: gpio@8b2c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2c000 0x1000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gmac0: ethernet@9840000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9840000 0x1000>,
<0x984300c 0x4>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH0_MAC_CLK>,
<&crg HISTB_ETH0_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 8>,
<&crg 0xcc 10>,
<&gmacphyrst 0>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
gmac1: ethernet@9841000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9841000 0x1000>,
<0x9843010 0x4>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH1_MAC_CLK>,
<&crg HISTB_ETH1_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 9>,
<&crg 0xcc 11>,
<&gmacphyrst 1>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
ir: ir@8001000 {
compatible = "hisilicon,hix5hd2-ir";
reg = <0x8001000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_IR_CLK>;
status = "disabled";
};
};
};

3
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@ -774,6 +774,7 @@ dwmmc_0: dwmmc0@f723d000 {
clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
reset-names = "reset";
bus-width = <0x8>;
vmmc-supply = <&ldo19>;
pinctrl-names = "default";
@ -797,6 +798,7 @@ dwmmc_1: dwmmc1@f723e000 {
clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
reset-names = "reset";
vqmmc-supply = <&ldo7>;
vmmc-supply = <&ldo10>;
bus-width = <0x4>;
@ -815,6 +817,7 @@ dwmmc_2: dwmmc2@f723f000 {
clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
reset-names = "reset";
bus-width = <0x4>;
broken-cd;
pinctrl-names = "default", "idle";

407
arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi Normal file
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@ -0,0 +1,407 @@
/*
* pinctrl dts fils for Hislicon HiKey960 development board
*
*/
#include <dt-bindings/pinctrl/hisi.h>
/ {
soc {
/* [IOMG_000, IOMG_123] */
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
pmx0: pinmux@e896c000 {
compatible = "pinctrl-single";
reg = <0x0 0xe896c000 0x0 0x1f0>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <
&range 0 7 0
&range 8 116 0>;
isp0_pmx_func: isp0_pmx_func {
pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */
0x064 MUX_M1 /* ISP_SCL0 */
0x068 MUX_M1 /* ISP_SDA0 */
>;
};
isp1_pmx_func: isp1_pmx_func {
pinctrl-single,pins = <
0x05c MUX_M1 /* ISP_CLK1 */
0x06c MUX_M1 /* ISP_SCL1 */
0x070 MUX_M1 /* ISP_SDA1 */
>;
};
i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = <
0x02c MUX_M1 /* I2C3_SCL */
0x030 MUX_M1 /* I2C3_SDA */
>;
};
i2c4_pmx_func: i2c4_pmx_func {
pinctrl-single,pins = <
0x090 MUX_M1 /* I2C4_SCL */
0x094 MUX_M1 /* I2C4_SDA */
>;
};
pcie_perstn_pmx_func: pcie_perstn_pmx_func {
pinctrl-single,pins = <
0x15c MUX_M1 /* PCIE_PERST_N */
>;
};
usbhub5734_pmx_func: usbhub5734_pmx_func {
pinctrl-single,pins = <
0x11c MUX_M0 /* GPIO_073 */
0x120 MUX_M0 /* GPIO_074 */
>;
};
spi1_pmx_func: spi1_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* SPI1_CLK */
0x038 MUX_M1 /* SPI1_DI */
0x03c MUX_M1 /* SPI1_DO */
0x040 MUX_M1 /* SPI1_CS_N */
>;
};
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0x0cc MUX_M2 /* UART0_RXD */
0x0d0 MUX_M2 /* UART0_TXD */
0x0d4 MUX_M2 /* UART0_RXD_M */
0x0d8 MUX_M2 /* UART0_TXD_M */
>;
};
uart1_pmx_func: uart1_pmx_func {
pinctrl-single,pins = <
0x0b0 MUX_M2 /* UART1_CTS_N */
0x0b4 MUX_M2 /* UART1_RTS_N */
0x0a8 MUX_M2 /* UART1_RXD */
0x0ac MUX_M2 /* UART1_TXD */
>;
};
uart2_pmx_func: uart2_pmx_func {
pinctrl-single,pins = <
0x0bc MUX_M2 /* UART2_CTS_N */
0x0c0 MUX_M2 /* UART2_RTS_N */
0x0c8 MUX_M2 /* UART2_RXD */
0x0c4 MUX_M2 /* UART2_TXD */
>;
};
uart3_pmx_func: uart3_pmx_func {
pinctrl-single,pins = <
0x0dc MUX_M1 /* UART3_CTS_N */
0x0e0 MUX_M1 /* UART3_RTS_N */
0x0e4 MUX_M1 /* UART3_RXD */
0x0e8 MUX_M1 /* UART3_TXD */
>;
};
uart4_pmx_func: uart4_pmx_func {
pinctrl-single,pins = <
0x0ec MUX_M1 /* UART4_CTS_N */
0x0f0 MUX_M1 /* UART4_RTS_N */
0x0f4 MUX_M1 /* UART4_RXD */
0x0f8 MUX_M1 /* UART4_TXD */
>;
};
uart5_pmx_func: uart5_pmx_func {
pinctrl-single,pins = <
0x0c4 MUX_M3 /* UART5_CTS_N */
0x0c8 MUX_M3 /* UART5_RTS_N */
0x0bc MUX_M3 /* UART5_RXD */
0x0c0 MUX_M3 /* UART5_TXD */
>;
};
uart6_pmx_func: uart6_pmx_func {
pinctrl-single,pins = <
0x0cc MUX_M1 /* UART6_CTS_N */
0x0d0 MUX_M1 /* UART6_RTS_N */
0x0d4 MUX_M1 /* UART6_RXD */
0x0d8 MUX_M1 /* UART6_TXD */
>;
};
};
/* [IOMG_MMC0_000, IOMG_MMC0_005] */
pmx1: pinmux@ff37e000 {
compatible = "pinctrl-single";
reg = <0x0 0xff37e000 0x0 0x18>;
#gpio-range-cells = <0x3>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 6 0>;
sd_pmx_func: sd_pmx_func {
pinctrl-single,pins = <
0x000 MUX_M1 /* SD_CLK */
0x004 MUX_M1 /* SD_CMD */
0x008 MUX_M1 /* SD_DATA0 */
0x00c MUX_M1 /* SD_DATA1 */
0x010 MUX_M1 /* SD_DATA2 */
0x014 MUX_M1 /* SD_DATA3 */
>;
};
};
/* [IOMG_FIX_000, IOMG_FIX_011] */
pmx2: pinmux@ff3b6000 {
compatible = "pinctrl-single";
reg = <0x0 0xff3b6000 0x0 0x30>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>;
spi3_pmx_func: spi3_pmx_func {
pinctrl-single,pins = <
0x008 MUX_M1 /* SPI3_CLK */
0x00c MUX_M1 /* SPI3_DI */
0x010 MUX_M1 /* SPI3_DO */
0x014 MUX_M1 /* SPI3_CS0_N */
>;
};
};
/* [IOMG_MMC1_000, IOMG_MMC1_005] */
pmx3: pinmux@ff3fd000 {
compatible = "pinctrl-single";
reg = <0x0 0xff3fd000 0x0 0x18>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 6 0>;
sdio_pmx_func: sdio_pmx_func {
pinctrl-single,pins = <
0x000 MUX_M1 /* SDIO_CLK */
0x004 MUX_M1 /* SDIO_CMD */
0x008 MUX_M1 /* SDIO_DATA0 */
0x00c MUX_M1 /* SDIO_DATA1 */
0x010 MUX_M1 /* SDIO_DATA2 */
0x014 MUX_M1 /* SDIO_DATA3 */
>;
};
};
/* [IOMG_AO_000, IOMG_AO_041] */
pmx4: pinmux@fff11000 {
compatible = "pinctrl-single";
reg = <0x0 0xfff11000 0x0 0xa8>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base in node, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 42 0>;
i2s2_pmx_func: i2s2_pmx_func {
pinctrl-single,pins = <
0x044 MUX_M1 /* I2S2_DI */
0x048 MUX_M1 /* I2S2_DO */
0x04c MUX_M1 /* I2S2_XCLK */
0x050 MUX_M1 /* I2S2_XFS */
>;
};
slimbus_pmx_func: slimbus_pmx_func {
pinctrl-single,pins = <
0x02c MUX_M1 /* SLIMBUS_CLK */
0x030 MUX_M1 /* SLIMBUS_DATA */
>;
};
i2c0_pmx_func: i2c0_pmx_func {
pinctrl-single,pins = <
0x014 MUX_M1 /* I2C0_SCL */
0x018 MUX_M1 /* I2C0_SDA */
>;
};
i2c1_pmx_func: i2c1_pmx_func {
pinctrl-single,pins = <
0x01c MUX_M1 /* I2C1_SCL */
0x020 MUX_M1 /* I2C1_SDA */
>;
};
i2c2_pmx_func: i2c2_pmx_func {
pinctrl-single,pins = <
0x024 MUX_M1 /* I2C2_SCL */
0x028 MUX_M1 /* I2C2_SDA */
>;
};
i2c7_pmx_func: i2c7_pmx_func {
pinctrl-single,pins = <
0x024 MUX_M3 /* I2C7_SCL */
0x028 MUX_M3 /* I2C7_SDA */
>;
};
spi2_pmx_func: spi2_pmx_func {
pinctrl-single,pins = <
0x08c MUX_M1 /* SPI2_CLK */
0x090 MUX_M1 /* SPI2_DI */
0x094 MUX_M1 /* SPI2_DO */
0x098 MUX_M1 /* SPI2_CS0_N */
>;
};
spi4_pmx_func: spi4_pmx_func {
pinctrl-single,pins = <
0x08c MUX_M4 /* SPI4_CLK */
0x090 MUX_M4 /* SPI4_DI */
0x094 MUX_M4 /* SPI4_DO */
0x098 MUX_M4 /* SPI4_CS0_N */
>;
};
i2s0_pmx_func: i2s0_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* I2S0_DI */
0x038 MUX_M1 /* I2S0_DO */
0x03c MUX_M1 /* I2S0_XCLK */
0x040 MUX_M1 /* I2S0_XFS */
>;
};
};
pmx5: pinmux@ff3fd800 {
compatible = "pinconf-single";
reg = <0x0 0xff3fd800 0x0 0x18>;
#pinctrl-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
sdio_clk_cfg_func: sdio_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SDIO_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_32MA
DRIVE6_MASK
>;
};
sdio_cfg_func: sdio_cfg_func {
pinctrl-single,pins = <
0x004 0x0 /* SDIO_CMD */
0x008 0x0 /* SDIO_DATA0 */
0x00c 0x0 /* SDIO_DATA1 */
0x010 0x0 /* SDIO_DATA2 */
0x014 0x0 /* SDIO_DATA3 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_19MA
DRIVE6_MASK
>;
};
};
pmx6: pinmux@ff37e800 {
compatible = "pinconf-single";
reg = <0x0 0xff37e800 0x0 0x18>;
#pinctrl-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
sd_clk_cfg_func: sd_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SD_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_32MA
DRIVE6_MASK
>;
};
sd_cfg_func: sd_cfg_func {
pinctrl-single,pins = <
0x004 0x0 /* SD_CMD */
0x008 0x0 /* SD_DATA0 */
0x00c 0x0 /* SD_DATA1 */
0x010 0x0 /* SD_DATA2 */
0x014 0x0 /* SD_DATA3 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_19MA
DRIVE6_MASK
>;
};
};
};
};

20
arch/arm64/boot/dts/hisilicon/hip07-d05.dts
View File

@ -64,3 +64,23 @@ &usb_ohci {
&usb_ehci {
status = "ok";
};
&eth0 {
status = "ok";
};
&eth1 {
status = "ok";
};
&eth2 {
status = "ok";
};
&eth3 {
status = "ok";
};
&sas1 {
status = "ok";
};

479
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@ -1014,6 +1014,34 @@ p0_mbigen_pcie_a: interrupt-controller@a0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xa0080000 0x0 0x10000>;
mbigen_pcie2_a: intc_pcie2_a {
msi-parent = <&p0_its_dsa_a 0x40087>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <10>;
};
mbigen_sas1: intc_sas1 {
msi-parent = <&p0_its_dsa_a 0x40000>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
mbigen_sas2: intc_sas2 {
msi-parent = <&p0_its_dsa_a 0x40040>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
mbigen_smmu_pcie: intc_smmu_pcie {
msi-parent = <&p0_its_dsa_a 0x40b0c>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
mbigen_usb: intc_usb {
msi-parent = <&p0_its_dsa_a 0x40080>;
interrupt-controller;
@ -1022,6 +1050,39 @@ mbigen_usb: intc_usb {
};
};
p0_mbigen_dsa_a: interrupt-controller@c0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xc0080000 0x0 0x10000>;
mbigen_dsaf0: intc_dsaf0 {
msi-parent = <&p0_its_dsa_a 0x40800>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <409>;
};
mbigen_dsa_roce: intc-roce {
msi-parent = <&p0_its_dsa_a 0x40B1E>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <34>;
};
mbigen_sas0: intc-sas0 {
msi-parent = <&p0_its_dsa_a 0x40900>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
mbigen_smmu_dsa: intc_smmu_dsa {
msi-parent = <&p0_its_dsa_a 0x40b20>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@ -1055,5 +1116,423 @@ usb_ehci: ehci@a7020000 {
dma-coherent;
status = "disabled";
};
peri_c_subctrl: sub_ctrl_c@60000000 {
compatible = "hisilicon,peri-subctrl","syscon";
reg = <0 0x60000000 0x0 0x10000>;
};
dsa_subctrl: dsa_subctrl@c0000000 {
compatible = "hisilicon,dsa-subctrl", "syscon";
reg = <0x0 0xc0000000 0x0 0x10000>;
};
pcie_subctl: pcie_subctl@a0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0x0 0xa0000000 0x0 0x10000>;
};
serdes_ctrl: sds_ctrl@c2200000 {
compatible = "syscon";
reg = <0 0xc2200000 0x0 0x80000>;
};
mdio@603c0000 {
compatible = "hisilicon,hns-mdio";
reg = <0x0 0x603c0000 0x0 0x1000>;
subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
0x531c 0x5a1c>;
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
dsaf0: dsa@c7000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;
reset-field-offset = <0>;
interrupts =
<576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
<581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
<586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
<591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
<596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
<960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
<965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
<970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
<975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
<980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
<985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
<990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
<995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
<1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
<1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
<1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
<1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
<1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
<1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
<1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
<1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
<1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
<1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
<1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
<1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
<1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
<1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
<1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
<1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
<1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
<1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
<1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
<1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
<1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
<1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
<1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
<1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
<1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
<1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
<1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
<1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
<1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
<1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
<1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
<1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
<1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
<1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
<1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
<1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
<1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
<1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
<1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
<1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
<1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
<1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
<1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
<1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
<1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
<1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
<1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
<1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
<1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
<1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
<1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
<1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
<1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
<1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
<1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
<1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
<1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
<1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
<1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
<1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
<1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
<1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
<1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
<1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
<1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
<1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
<1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
<1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
<1340 1>, <1341 1>, <1342 1>, <1343 1>;
desc-num = <0x400>;
buf-size = <0x1000>;
dma-coherent;
port@0 {
reg = <0>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <0>;
port-mode-offset = <0>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "fiber";
};
port@1 {
reg = <1>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <1>;
port-mode-offset = <1>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "fiber";
};
port@4 {
reg = <4>;
phy-handle = <&phy0>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "copper";
};
port@5 {
reg = <5>;
phy-handle = <&phy1>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "copper";
};
};
eth0: ethernet@4{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth1: ethernet@5{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth2: ethernet@0{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth3: ethernet@1{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
infiniband@c4000000 {
compatible = "hisilicon,hns-roce-v1";
reg = <0x0 0xc4000000 0x0 0x100000>;
dma-coherent;
eth-handle = <&eth2 &eth3 0 0 &eth0 &eth1>;
dsaf-handle = <&dsaf0>;
node-guid = [00 9A CD 00 00 01 02 03];
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mbigen_dsa_roce>;
interrupts = <722 1>,
<723 1>,
<724 1>,
<725 1>,
<726 1>,
<727 1>,
<728 1>,
<729 1>,
<730 1>,
<731 1>,
<732 1>,
<733 1>,
<734 1>,
<735 1>,
<736 1>,
<737 1>,
<738 1>,
<739 1>,
<740 1>,
<741 1>,
<742 1>,
<743 1>,
<744 1>,
<745 1>,
<746 1>,
<747 1>,
<748 1>,
<749 1>,
<750 1>,
<751 1>,
<752 1>,
<753 1>,
<785 1>,
<754 4>;
interrupt-names = "hns-roce-comp-0",
"hns-roce-comp-1",
"hns-roce-comp-2",
"hns-roce-comp-3",
"hns-roce-comp-4",
"hns-roce-comp-5",
"hns-roce-comp-6",
"hns-roce-comp-7",
"hns-roce-comp-8",
"hns-roce-comp-9",
"hns-roce-comp-10",
"hns-roce-comp-11",
"hns-roce-comp-12",
"hns-roce-comp-13",
"hns-roce-comp-14",
"hns-roce-comp-15",
"hns-roce-comp-16",
"hns-roce-comp-17",
"hns-roce-comp-18",
"hns-roce-comp-19",
"hns-roce-comp-20",
"hns-roce-comp-21",
"hns-roce-comp-22",
"hns-roce-comp-23",
"hns-roce-comp-24",
"hns-roce-comp-25",
"hns-roce-comp-26",
"hns-roce-comp-27",
"hns-roce-comp-28",
"hns-roce-comp-29",
"hns-roce-comp-30",
"hns-roce-comp-31",
"hns-roce-async",
"hns-roce-common";
};
sas0: sas@c3000000 {
compatible = "hisilicon,hip07-sas-v2";
reg = <0 0xc3000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&dsa_subctrl>;
ctrl-reset-reg = <0xa60>;
ctrl-reset-sts-reg = <0x5a30>;
ctrl-clock-ena-reg = <0x338>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
interrupt-parent = <&mbigen_sas0>;
interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
<74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
<79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
<84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
<89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
<94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
<99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
<104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
<109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
<114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
<119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
<124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
<129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
<134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
<139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
<144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
<149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
<154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
<159 4>,<601 1>,<602 1>,<603 1>,<604 1>,
<605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
<610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
<615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
<620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
<625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
<630 1>,<631 1>,<632 1>;
status = "disabled";
};
sas1: sas@a2000000 {
compatible = "hisilicon,hip07-sas-v2";
reg = <0 0xa2000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&pcie_subctl>;
hip06-sas-v2-quirk-amt;
ctrl-reset-reg = <0xa18>;
ctrl-reset-sts-reg = <0x5a0c>;
ctrl-clock-ena-reg = <0x318>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
interrupt-parent = <&mbigen_sas1>;
interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
<74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
<79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
<84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
<89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
<94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
<99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
<104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
<109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
<114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
<119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
<124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
<129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
<134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
<139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
<144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
<149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
<154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
<159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
<580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
<585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
<590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
<595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
<600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
<605 1>,<606 1>,<607 1>;
status = "disabled";
};
sas2: sas@a3000000 {
compatible = "hisilicon,hip07-sas-v2";
reg = <0 0xa3000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&pcie_subctl>;
ctrl-reset-reg = <0xae0>;
ctrl-reset-sts-reg = <0x5a70>;
ctrl-clock-ena-reg = <0x3a8>;
queue-count = <16>;
phy-count = <9>;
dma-coherent;
interrupt-parent = <&mbigen_sas2>;
interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
<197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
<202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
<207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
<212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
<217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
<222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
<227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
<232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
<237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
<242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
<247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
<252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
<257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
<262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
<267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
<272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
<277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
<282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
<287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
<612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
<617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
<622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
<627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
<632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
<637 1>,<638 1>,<639 1>;
status = "disabled";
};
};
};

15
include/dt-bindings/pinctrl/hisi.h
View File

@ -56,4 +56,19 @@
#define DRIVE4_08MA (4 << 4)
#define DRIVE4_10MA (6 << 4)
/* drive strength definition for hi3660 */
#define DRIVE6_MASK (15 << 4)
#define DRIVE6_04MA (0 << 4)
#define DRIVE6_12MA (4 << 4)
#define DRIVE6_19MA (8 << 4)
#define DRIVE6_27MA (10 << 4)
#define DRIVE6_32MA (15 << 4)
#define DRIVE7_02MA (0 << 4)
#define DRIVE7_04MA (1 << 4)
#define DRIVE7_06MA (2 << 4)
#define DRIVE7_08MA (3 << 4)
#define DRIVE7_10MA (4 << 4)
#define DRIVE7_12MA (5 << 4)
#define DRIVE7_14MA (6 << 4)
#define DRIVE7_16MA (7 << 4)
#endif