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i915/dp/fec: Cache the FEC_CAPABLE DPCD register
Similar to DSC DPCD registers, let us cache FEC_CAPABLE register to avoid using stale values. With this we can avoid aux reads everytime and instead read the cached values. v2: Avoid using memset and array for a single field. (Manasi,Jani) v3: Print FEC CAPABILITY value. (Manasi) Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102041455.15818-1-anusha.srivatsa@intel.com
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@ -3954,6 +3954,9 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
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*/
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memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
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/* Clear fec_capable to avoid using stale values */
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intel_dp->fec_capable = 0;
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/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
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if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
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intel_dp->edp_dpcd[0] >= DP_EDP_14) {
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@ -3966,6 +3969,15 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
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DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
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(int)sizeof(intel_dp->dsc_dpcd),
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intel_dp->dsc_dpcd);
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/* FEC is supported only on DP 1.4 */
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if (!intel_dp_is_edp(intel_dp)) {
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if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
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&intel_dp->fec_capable) < 0)
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DRM_ERROR("Failed to read FEC DPCD register\n");
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DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
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intel_dp->fec_capable);
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}
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}
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}
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@ -1114,6 +1114,7 @@ struct intel_dp {
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uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
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uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
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u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
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u8 fec_capable;
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/* source rates */
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int num_source_rates;
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const int *source_rates;
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