mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 12:00:58 +07:00
Merge remote-tracking branch 'torvalds/master' into perf/urgent
To get some newer headers that got out of sync with the copies in tools/ so that we can try to have the tools/perf/ build clean for v5.8 with fewer pull requests. Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Arnaldo Carvalho de Melo
commit
08a7c7772b
@ -1,3 +1,9 @@
|
||||
What: sys/bus/dsa/devices/dsa<m>/version
|
||||
Date: Apr 15, 2020
|
||||
KernelVersion: 5.8.0
|
||||
Contact: dmaengine@vger.kernel.org
|
||||
Description: The hardware version number.
|
||||
|
||||
What: sys/bus/dsa/devices/dsa<m>/cdev_major
|
||||
Date: Oct 25, 2019
|
||||
KernelVersion: 5.6.0
|
||||
|
||||
@ -74,6 +74,21 @@ Description:
|
||||
Access: Read, Write
|
||||
Valid values: 0 - 100 (percent)
|
||||
|
||||
What: /sys/class/power_supply/<supply_name>/capacity_error_margin
|
||||
Date: April 2019
|
||||
Contact: linux-pm@vger.kernel.org
|
||||
Description:
|
||||
Battery capacity measurement becomes unreliable without
|
||||
recalibration. This values provides the maximum error
|
||||
margin expected to exist by the fuel gauge in percent.
|
||||
Values close to 0% will be returned after (re-)calibration
|
||||
has happened. Over time the error margin will increase.
|
||||
100% means, that the capacity related values are basically
|
||||
completely useless.
|
||||
|
||||
Access: Read
|
||||
Valid values: 0 - 100 (percent)
|
||||
|
||||
What: /sys/class/power_supply/<supply_name>/capacity_level
|
||||
Date: June 2009
|
||||
Contact: linux-pm@vger.kernel.org
|
||||
@ -190,7 +205,7 @@ Description:
|
||||
Valid values: "Unknown", "Good", "Overheat", "Dead",
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"Over voltage", "Unspecified failure", "Cold",
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"Watchdog timer expire", "Safety timer expire",
|
||||
"Over current"
|
||||
"Over current", "Calibration required"
|
||||
|
||||
What: /sys/class/power_supply/<supply_name>/precharge_current
|
||||
Date: June 2017
|
||||
@ -665,3 +680,31 @@ Description:
|
||||
Valid values:
|
||||
- 1: enabled
|
||||
- 0: disabled
|
||||
|
||||
What: /sys/class/power_supply/<supply_name>/manufacture_year
|
||||
Date: January 2020
|
||||
Contact: linux-pm@vger.kernel.org
|
||||
Description:
|
||||
Reports the year (following Gregorian calendar) when the device has been
|
||||
manufactured.
|
||||
|
||||
Access: Read
|
||||
Valid values: Reported as integer
|
||||
|
||||
What: /sys/class/power_supply/<supply_name>/manufacture_month
|
||||
Date: January 2020
|
||||
Contact: linux-pm@vger.kernel.org
|
||||
Description:
|
||||
Reports the month when the device has been manufactured.
|
||||
|
||||
Access: Read
|
||||
Valid values: 1-12
|
||||
|
||||
What: /sys/class/power_supply/<supply_name>/manufacture_day
|
||||
Date: January 2020
|
||||
Contact: linux-pm@vger.kernel.org
|
||||
Description:
|
||||
Reports the day of month when the device has been manufactured.
|
||||
|
||||
Access: Read
|
||||
Valid values: 1-31
|
||||
|
||||
@ -486,6 +486,7 @@ What: /sys/devices/system/cpu/vulnerabilities
|
||||
/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
|
||||
/sys/devices/system/cpu/vulnerabilities/l1tf
|
||||
/sys/devices/system/cpu/vulnerabilities/mds
|
||||
/sys/devices/system/cpu/vulnerabilities/srbds
|
||||
/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
|
||||
/sys/devices/system/cpu/vulnerabilities/itlb_multihit
|
||||
Date: January 2018
|
||||
|
||||
@ -323,3 +323,27 @@ What: /sys/fs/f2fs/<disk>/mounted_time_sec
|
||||
Date: February 2020
|
||||
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
|
||||
Description: Show the mounted time in secs of this partition.
|
||||
|
||||
What: /sys/fs/f2fs/<disk>/data_io_flag
|
||||
Date: April 2020
|
||||
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
|
||||
Description: Give a way to attach REQ_META|FUA to data writes
|
||||
given temperature-based bits. Now the bits indicate:
|
||||
* REQ_META | REQ_FUA |
|
||||
* 5 | 4 | 3 | 2 | 1 | 0 |
|
||||
* Cold | Warm | Hot | Cold | Warm | Hot |
|
||||
|
||||
What: /sys/fs/f2fs/<disk>/node_io_flag
|
||||
Date: June 2020
|
||||
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
|
||||
Description: Give a way to attach REQ_META|FUA to node writes
|
||||
given temperature-based bits. Now the bits indicate:
|
||||
* REQ_META | REQ_FUA |
|
||||
* 5 | 4 | 3 | 2 | 1 | 0 |
|
||||
* Cold | Warm | Hot | Cold | Warm | Hot |
|
||||
|
||||
What: /sys/fs/f2fs/<disk>/iostat_period_ms
|
||||
Date: April 2020
|
||||
Contact: "Daeho Jeong" <daehojeong@google.com>
|
||||
Description: Give a way to change iostat_period time. 3secs by default.
|
||||
The new iostat trace gives stats gap given the period.
|
||||
|
||||
@ -9,5 +9,5 @@ scale down to smaller sizes and are better for letterheads or whatever
|
||||
you want to use it for: for the full range of logos take a look at
|
||||
Larry's web-page:
|
||||
|
||||
http://www.isc.tamu.edu/~lewing/linux/
|
||||
https://www.isc.tamu.edu/~lewing/linux/
|
||||
|
||||
|
||||
@ -27,29 +27,29 @@ Where is documentation?
|
||||
=======================
|
||||
|
||||
User <-> Kernel interface documentation is available at
|
||||
http://tomoyo.osdn.jp/2.5/policy-specification/index.html .
|
||||
https://tomoyo.osdn.jp/2.5/policy-specification/index.html .
|
||||
|
||||
Materials we prepared for seminars and symposiums are available at
|
||||
http://osdn.jp/projects/tomoyo/docs/?category_id=532&language_id=1 .
|
||||
https://osdn.jp/projects/tomoyo/docs/?category_id=532&language_id=1 .
|
||||
Below lists are chosen from three aspects.
|
||||
|
||||
What is TOMOYO?
|
||||
TOMOYO Linux Overview
|
||||
http://osdn.jp/projects/tomoyo/docs/lca2009-takeda.pdf
|
||||
https://osdn.jp/projects/tomoyo/docs/lca2009-takeda.pdf
|
||||
TOMOYO Linux: pragmatic and manageable security for Linux
|
||||
http://osdn.jp/projects/tomoyo/docs/freedomhectaipei-tomoyo.pdf
|
||||
https://osdn.jp/projects/tomoyo/docs/freedomhectaipei-tomoyo.pdf
|
||||
TOMOYO Linux: A Practical Method to Understand and Protect Your Own Linux Box
|
||||
http://osdn.jp/projects/tomoyo/docs/PacSec2007-en-no-demo.pdf
|
||||
https://osdn.jp/projects/tomoyo/docs/PacSec2007-en-no-demo.pdf
|
||||
|
||||
What can TOMOYO do?
|
||||
Deep inside TOMOYO Linux
|
||||
http://osdn.jp/projects/tomoyo/docs/lca2009-kumaneko.pdf
|
||||
https://osdn.jp/projects/tomoyo/docs/lca2009-kumaneko.pdf
|
||||
The role of "pathname based access control" in security.
|
||||
http://osdn.jp/projects/tomoyo/docs/lfj2008-bof.pdf
|
||||
https://osdn.jp/projects/tomoyo/docs/lfj2008-bof.pdf
|
||||
|
||||
History of TOMOYO?
|
||||
Realities of Mainlining
|
||||
http://osdn.jp/projects/tomoyo/docs/lfj2008.pdf
|
||||
https://osdn.jp/projects/tomoyo/docs/lfj2008.pdf
|
||||
|
||||
What is future plan?
|
||||
====================
|
||||
|
||||
@ -102,7 +102,7 @@ Where to retrieve userspace tools
|
||||
=================================
|
||||
|
||||
iasl and acpixtract are part of Intel's ACPICA project:
|
||||
http://acpica.org/
|
||||
https://acpica.org/
|
||||
|
||||
and should be packaged by distributions (for example in the acpica package
|
||||
on SUSE).
|
||||
|
||||
@ -7,9 +7,9 @@ nice if you could use them as cache... Hence bcache.
|
||||
|
||||
Wiki and git repositories are at:
|
||||
|
||||
- http://bcache.evilpiepirate.org
|
||||
- https://bcache.evilpiepirate.org
|
||||
- http://evilpiepirate.org/git/linux-bcache.git
|
||||
- http://evilpiepirate.org/git/bcache-tools.git
|
||||
- https://evilpiepirate.org/git/bcache-tools.git
|
||||
|
||||
It's designed around the performance characteristics of SSDs - it only allocates
|
||||
in erase block sized buckets, and it uses a hybrid btree/log to track cached
|
||||
|
||||
@ -17,7 +17,7 @@ Specifically explore the sections titled "CHAR and MISC DRIVERS", and
|
||||
to involve for character and block devices.
|
||||
|
||||
This document is included by reference into the Filesystem Hierarchy
|
||||
Standard (FHS). The FHS is available from http://www.pathname.com/fhs/.
|
||||
Standard (FHS). The FHS is available from https://www.pathname.com/fhs/.
|
||||
|
||||
Allocations marked (68k/Amiga) apply to Linux/68k on the Amiga
|
||||
platform only. Allocations marked (68k/Atari) apply to Linux/68k on
|
||||
|
||||
@ -14,3 +14,4 @@ are configurable at compile, boot or run time.
|
||||
mds
|
||||
tsx_async_abort
|
||||
multihit.rst
|
||||
special-register-buffer-data-sampling.rst
|
||||
|
||||
@ -0,0 +1,149 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
SRBDS - Special Register Buffer Data Sampling
|
||||
=============================================
|
||||
|
||||
SRBDS is a hardware vulnerability that allows MDS :doc:`mds` techniques to
|
||||
infer values returned from special register accesses. Special register
|
||||
accesses are accesses to off core registers. According to Intel's evaluation,
|
||||
the special register reads that have a security expectation of privacy are
|
||||
RDRAND, RDSEED and SGX EGETKEY.
|
||||
|
||||
When RDRAND, RDSEED and EGETKEY instructions are used, the data is moved
|
||||
to the core through the special register mechanism that is susceptible
|
||||
to MDS attacks.
|
||||
|
||||
Affected processors
|
||||
--------------------
|
||||
Core models (desktop, mobile, Xeon-E3) that implement RDRAND and/or RDSEED may
|
||||
be affected.
|
||||
|
||||
A processor is affected by SRBDS if its Family_Model and stepping is
|
||||
in the following list, with the exception of the listed processors
|
||||
exporting MDS_NO while Intel TSX is available yet not enabled. The
|
||||
latter class of processors are only affected when Intel TSX is enabled
|
||||
by software using TSX_CTRL_MSR otherwise they are not affected.
|
||||
|
||||
============= ============ ========
|
||||
common name Family_Model Stepping
|
||||
============= ============ ========
|
||||
IvyBridge 06_3AH All
|
||||
|
||||
Haswell 06_3CH All
|
||||
Haswell_L 06_45H All
|
||||
Haswell_G 06_46H All
|
||||
|
||||
Broadwell_G 06_47H All
|
||||
Broadwell 06_3DH All
|
||||
|
||||
Skylake_L 06_4EH All
|
||||
Skylake 06_5EH All
|
||||
|
||||
Kabylake_L 06_8EH <= 0xC
|
||||
Kabylake 06_9EH <= 0xD
|
||||
============= ============ ========
|
||||
|
||||
Related CVEs
|
||||
------------
|
||||
|
||||
The following CVE entry is related to this SRBDS issue:
|
||||
|
||||
============== ===== =====================================
|
||||
CVE-2020-0543 SRBDS Special Register Buffer Data Sampling
|
||||
============== ===== =====================================
|
||||
|
||||
Attack scenarios
|
||||
----------------
|
||||
An unprivileged user can extract values returned from RDRAND and RDSEED
|
||||
executed on another core or sibling thread using MDS techniques.
|
||||
|
||||
|
||||
Mitigation mechanism
|
||||
-------------------
|
||||
Intel will release microcode updates that modify the RDRAND, RDSEED, and
|
||||
EGETKEY instructions to overwrite secret special register data in the shared
|
||||
staging buffer before the secret data can be accessed by another logical
|
||||
processor.
|
||||
|
||||
During execution of the RDRAND, RDSEED, or EGETKEY instructions, off-core
|
||||
accesses from other logical processors will be delayed until the special
|
||||
register read is complete and the secret data in the shared staging buffer is
|
||||
overwritten.
|
||||
|
||||
This has three effects on performance:
|
||||
|
||||
#. RDRAND, RDSEED, or EGETKEY instructions have higher latency.
|
||||
|
||||
#. Executing RDRAND at the same time on multiple logical processors will be
|
||||
serialized, resulting in an overall reduction in the maximum RDRAND
|
||||
bandwidth.
|
||||
|
||||
#. Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other
|
||||
logical processors that miss their core caches, with an impact similar to
|
||||
legacy locked cache-line-split accesses.
|
||||
|
||||
The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
|
||||
the mitigation for RDRAND and RDSEED instructions executed outside of Intel
|
||||
Software Guard Extensions (Intel SGX) enclaves. On logical processors that
|
||||
disable the mitigation using this opt-out mechanism, RDRAND and RDSEED do not
|
||||
take longer to execute and do not impact performance of sibling logical
|
||||
processors memory accesses. The opt-out mechanism does not affect Intel SGX
|
||||
enclaves (including execution of RDRAND or RDSEED inside an enclave, as well
|
||||
as EGETKEY execution).
|
||||
|
||||
IA32_MCU_OPT_CTRL MSR Definition
|
||||
--------------------------------
|
||||
Along with the mitigation for this issue, Intel added a new thread-scope
|
||||
IA32_MCU_OPT_CTRL MSR, (address 0x123). The presence of this MSR and
|
||||
RNGDS_MITG_DIS (bit 0) is enumerated by CPUID.(EAX=07H,ECX=0).EDX[SRBDS_CTRL =
|
||||
9]==1. This MSR is introduced through the microcode update.
|
||||
|
||||
Setting IA32_MCU_OPT_CTRL[0] (RNGDS_MITG_DIS) to 1 for a logical processor
|
||||
disables the mitigation for RDRAND and RDSEED executed outside of an Intel SGX
|
||||
enclave on that logical processor. Opting out of the mitigation for a
|
||||
particular logical processor does not affect the RDRAND and RDSEED mitigations
|
||||
for other logical processors.
|
||||
|
||||
Note that inside of an Intel SGX enclave, the mitigation is applied regardless
|
||||
of the value of RNGDS_MITG_DS.
|
||||
|
||||
Mitigation control on the kernel command line
|
||||
---------------------------------------------
|
||||
The kernel command line allows control over the SRBDS mitigation at boot time
|
||||
with the option "srbds=". The option for this is:
|
||||
|
||||
============= =============================================================
|
||||
off This option disables SRBDS mitigation for RDRAND and RDSEED on
|
||||
affected platforms.
|
||||
============= =============================================================
|
||||
|
||||
SRBDS System Information
|
||||
-----------------------
|
||||
The Linux kernel provides vulnerability status information through sysfs. For
|
||||
SRBDS this can be accessed by the following sysfs file:
|
||||
/sys/devices/system/cpu/vulnerabilities/srbds
|
||||
|
||||
The possible values contained in this file are:
|
||||
|
||||
============================== =============================================
|
||||
Not affected Processor not vulnerable
|
||||
Vulnerable Processor vulnerable and mitigation disabled
|
||||
Vulnerable: No microcode Processor vulnerable and microcode is missing
|
||||
mitigation
|
||||
Mitigation: Microcode Processor is vulnerable and mitigation is in
|
||||
effect.
|
||||
Mitigation: TSX disabled Processor is only vulnerable when TSX is
|
||||
enabled while this system was booted with TSX
|
||||
disabled.
|
||||
Unknown: Dependent on
|
||||
hypervisor status Running on virtual guest processor that is
|
||||
affected but with no way to know if host
|
||||
processor is mitigated or vulnerable.
|
||||
============================== =============================================
|
||||
|
||||
SRBDS Default mitigation
|
||||
------------------------
|
||||
This new microcode serializes processor access during execution of RDRAND,
|
||||
RDSEED ensures that the shared buffer is overwritten before it is released for
|
||||
reuse. Use the "srbds=off" kernel command line to disable the mitigation for
|
||||
RDRAND and RDSEED.
|
||||
@ -376,7 +376,7 @@ Resources
|
||||
---------
|
||||
|
||||
.. [#f1] Almesberger, Werner; "Booting Linux: The History and the Future"
|
||||
http://www.almesberger.net/cv/papers/ols2k-9.ps.gz
|
||||
https://www.almesberger.net/cv/papers/ols2k-9.ps.gz
|
||||
.. [#f2] newlib package (experimental), with initrd example
|
||||
https://www.sourceware.org/newlib/
|
||||
.. [#f3] util-linux: Miscellaneous utilities for Linux
|
||||
|
||||
@ -4837,6 +4837,26 @@
|
||||
the kernel will oops in either "warn" or "fatal"
|
||||
mode.
|
||||
|
||||
srbds= [X86,INTEL]
|
||||
Control the Special Register Buffer Data Sampling
|
||||
(SRBDS) mitigation.
|
||||
|
||||
Certain CPUs are vulnerable to an MDS-like
|
||||
exploit which can leak bits from the random
|
||||
number generator.
|
||||
|
||||
By default, this issue is mitigated by
|
||||
microcode. However, the microcode fix can cause
|
||||
the RDRAND and RDSEED instructions to become
|
||||
much slower. Among other effects, this will
|
||||
result in reduced throughput from /dev/urandom.
|
||||
|
||||
The microcode mitigation can be disabled with
|
||||
the following option:
|
||||
|
||||
off: Disable mitigation and remove
|
||||
performance impact to RDRAND and RDSEED
|
||||
|
||||
srcutree.counter_wrap_check [KNL]
|
||||
Specifies how frequently to check for
|
||||
grace-period sequence counter wrap for the
|
||||
|
||||
@ -5,7 +5,7 @@ Boot time assembly of RAID arrays
|
||||
---------------------------------
|
||||
|
||||
Tools that manage md devices can be found at
|
||||
http://www.kernel.org/pub/linux/utils/raid/
|
||||
https://www.kernel.org/pub/linux/utils/raid/
|
||||
|
||||
|
||||
You can boot with your md device with the following kernel command
|
||||
|
||||
@ -364,19 +364,19 @@ follows:
|
||||
|
||||
2) for querying the policy, we do not need to take an extra reference on the
|
||||
target task's task policy nor vma policies because we always acquire the
|
||||
task's mm's mmap_sem for read during the query. The set_mempolicy() and
|
||||
mbind() APIs [see below] always acquire the mmap_sem for write when
|
||||
task's mm's mmap_lock for read during the query. The set_mempolicy() and
|
||||
mbind() APIs [see below] always acquire the mmap_lock for write when
|
||||
installing or replacing task or vma policies. Thus, there is no possibility
|
||||
of a task or thread freeing a policy while another task or thread is
|
||||
querying it.
|
||||
|
||||
3) Page allocation usage of task or vma policy occurs in the fault path where
|
||||
we hold them mmap_sem for read. Again, because replacing the task or vma
|
||||
policy requires that the mmap_sem be held for write, the policy can't be
|
||||
we hold them mmap_lock for read. Again, because replacing the task or vma
|
||||
policy requires that the mmap_lock be held for write, the policy can't be
|
||||
freed out from under us while we're using it for page allocation.
|
||||
|
||||
4) Shared policies require special consideration. One task can replace a
|
||||
shared memory policy while another task, with a distinct mmap_sem, is
|
||||
shared memory policy while another task, with a distinct mmap_lock, is
|
||||
querying or allocating a page based on the policy. To resolve this
|
||||
potential race, the shared policy infrastructure adds an extra reference
|
||||
to the shared policy during lookup while holding a spin lock on the shared
|
||||
|
||||
@ -33,7 +33,7 @@ memory ranges) provides two primary functionalities:
|
||||
The real advantage of userfaults if compared to regular virtual memory
|
||||
management of mremap/mprotect is that the userfaults in all their
|
||||
operations never involve heavyweight structures like vmas (in fact the
|
||||
``userfaultfd`` runtime load never takes the mmap_sem for writing).
|
||||
``userfaultfd`` runtime load never takes the mmap_lock for writing).
|
||||
|
||||
Vmas are not suitable for page- (or hugepage) granular fault tracking
|
||||
when dealing with virtual address spaces that could span
|
||||
|
||||
@ -12,11 +12,11 @@ other program after you have done the following:
|
||||
a binary package, a source tarball or by installing from Git. Binary
|
||||
packages for several distributions can be found at:
|
||||
|
||||
http://www.mono-project.com/download/
|
||||
https://www.mono-project.com/download/
|
||||
|
||||
Instructions for compiling Mono can be found at:
|
||||
|
||||
http://www.mono-project.com/docs/compiling-mono/linux/
|
||||
https://www.mono-project.com/docs/compiling-mono/linux/
|
||||
|
||||
Once the Mono CLR support has been installed, just check that
|
||||
``/usr/bin/mono`` (which could be located elsewhere, for example
|
||||
|
||||
@ -75,7 +75,7 @@ Tips for reporting bugs
|
||||
|
||||
If you haven't reported a bug before, please read:
|
||||
|
||||
http://www.chiark.greenend.org.uk/~sgtatham/bugs.html
|
||||
https://www.chiark.greenend.org.uk/~sgtatham/bugs.html
|
||||
|
||||
http://www.catb.org/esr/faqs/smart-questions.html
|
||||
|
||||
|
||||
@ -114,7 +114,7 @@ Unicode practice.
|
||||
This range is now officially managed by the ConScript Unicode
|
||||
Registry. The normative reference is at:
|
||||
|
||||
http://www.evertype.com/standards/csur/klingon.html
|
||||
https://www.evertype.com/standards/csur/klingon.html
|
||||
|
||||
Klingon has an alphabet of 26 characters, a positional numeric writing
|
||||
system with 10 digits, and is written left-to-right, top-to-bottom.
|
||||
@ -178,7 +178,7 @@ fictional and artificial scripts has been established by John Cowan
|
||||
<jcowan@reutershealth.com> and Michael Everson <everson@evertype.com>.
|
||||
The ConScript Unicode Registry is accessible at:
|
||||
|
||||
http://www.evertype.com/standards/csur/
|
||||
https://www.evertype.com/standards/csur/
|
||||
|
||||
The ranges used fall at the low end of the End User Zone and can hence
|
||||
not be normatively assigned, but it is recommended that people who
|
||||
|
||||
@ -538,7 +538,7 @@ epub_exclude_files = ['search.html']
|
||||
# Grouping the document tree into PDF files. List of tuples
|
||||
# (source start file, target name, title, author, options).
|
||||
#
|
||||
# See the Sphinx chapter of http://ralsina.me/static/manual.pdf
|
||||
# See the Sphinx chapter of https://ralsina.me/static/manual.pdf
|
||||
#
|
||||
# FIXME: Do not add the index file here; the result will be too big. Adding
|
||||
# multiple PDF files here actually tries to get the cross-referencing right
|
||||
|
||||
@ -36,10 +36,10 @@ This document covers use of the Linux rbtree implementation. For more
|
||||
information on the nature and implementation of Red Black Trees, see:
|
||||
|
||||
Linux Weekly News article on red-black trees
|
||||
http://lwn.net/Articles/184495/
|
||||
https://lwn.net/Articles/184495/
|
||||
|
||||
Wikipedia entry on red-black trees
|
||||
http://en.wikipedia.org/wiki/Red-black_tree
|
||||
https://en.wikipedia.org/wiki/Red-black_tree
|
||||
|
||||
Linux implementation of red-black trees
|
||||
---------------------------------------
|
||||
|
||||
@ -14,7 +14,7 @@ many uses in kernel development, including the application of complex,
|
||||
tree-wide patches and detection of problematic programming patterns.
|
||||
|
||||
Getting Coccinelle
|
||||
-------------------
|
||||
------------------
|
||||
|
||||
The semantic patches included in the kernel use features and options
|
||||
which are provided by Coccinelle version 1.0.0-rc11 and above.
|
||||
@ -56,7 +56,7 @@ found at:
|
||||
https://github.com/coccinelle/coccinelle/blob/master/install.txt
|
||||
|
||||
Supplemental documentation
|
||||
---------------------------
|
||||
--------------------------
|
||||
|
||||
For supplemental documentation refer to the wiki:
|
||||
|
||||
@ -128,7 +128,7 @@ To enable verbose messages set the V= variable, for example::
|
||||
make coccicheck MODE=report V=1
|
||||
|
||||
Coccinelle parallelization
|
||||
---------------------------
|
||||
--------------------------
|
||||
|
||||
By default, coccicheck tries to run as parallel as possible. To change
|
||||
the parallelism, set the J= variable. For example, to run across 4 CPUs::
|
||||
@ -333,7 +333,7 @@ as an example if requiring at least Coccinelle >= 1.0.5::
|
||||
// Requires: 1.0.5
|
||||
|
||||
Proposing new semantic patches
|
||||
-------------------------------
|
||||
------------------------------
|
||||
|
||||
New semantic patches can be proposed and submitted by kernel
|
||||
developers. For sake of clarity, they should be organized in the
|
||||
|
||||
@ -24,7 +24,7 @@ Setup
|
||||
|
||||
- Create a virtual Linux machine for QEMU/KVM (see www.linux-kvm.org and
|
||||
www.qemu.org for more details). For cross-development,
|
||||
http://landley.net/aboriginal/bin keeps a pool of machine images and
|
||||
https://landley.net/aboriginal/bin keeps a pool of machine images and
|
||||
toolchains that can be helpful to start from.
|
||||
|
||||
- Build the kernel with CONFIG_GDB_SCRIPTS enabled, but leave
|
||||
|
||||
@ -21,6 +21,7 @@ whole; patches welcome!
|
||||
kasan
|
||||
ubsan
|
||||
kmemleak
|
||||
kcsan
|
||||
gdb-kernel-debugging
|
||||
kgdb
|
||||
kselftest
|
||||
|
||||
321
Documentation/dev-tools/kcsan.rst
Normal file
321
Documentation/dev-tools/kcsan.rst
Normal file
@ -0,0 +1,321 @@
|
||||
The Kernel Concurrency Sanitizer (KCSAN)
|
||||
========================================
|
||||
|
||||
The Kernel Concurrency Sanitizer (KCSAN) is a dynamic race detector, which
|
||||
relies on compile-time instrumentation, and uses a watchpoint-based sampling
|
||||
approach to detect races. KCSAN's primary purpose is to detect `data races`_.
|
||||
|
||||
Usage
|
||||
-----
|
||||
|
||||
KCSAN requires Clang version 11 or later.
|
||||
|
||||
To enable KCSAN configure the kernel with::
|
||||
|
||||
CONFIG_KCSAN = y
|
||||
|
||||
KCSAN provides several other configuration options to customize behaviour (see
|
||||
the respective help text in ``lib/Kconfig.kcsan`` for more info).
|
||||
|
||||
Error reports
|
||||
~~~~~~~~~~~~~
|
||||
|
||||
A typical data race report looks like this::
|
||||
|
||||
==================================================================
|
||||
BUG: KCSAN: data-race in generic_permission / kernfs_refresh_inode
|
||||
|
||||
write to 0xffff8fee4c40700c of 4 bytes by task 175 on cpu 4:
|
||||
kernfs_refresh_inode+0x70/0x170
|
||||
kernfs_iop_permission+0x4f/0x90
|
||||
inode_permission+0x190/0x200
|
||||
link_path_walk.part.0+0x503/0x8e0
|
||||
path_lookupat.isra.0+0x69/0x4d0
|
||||
filename_lookup+0x136/0x280
|
||||
user_path_at_empty+0x47/0x60
|
||||
vfs_statx+0x9b/0x130
|
||||
__do_sys_newlstat+0x50/0xb0
|
||||
__x64_sys_newlstat+0x37/0x50
|
||||
do_syscall_64+0x85/0x260
|
||||
entry_SYSCALL_64_after_hwframe+0x44/0xa9
|
||||
|
||||
read to 0xffff8fee4c40700c of 4 bytes by task 166 on cpu 6:
|
||||
generic_permission+0x5b/0x2a0
|
||||
kernfs_iop_permission+0x66/0x90
|
||||
inode_permission+0x190/0x200
|
||||
link_path_walk.part.0+0x503/0x8e0
|
||||
path_lookupat.isra.0+0x69/0x4d0
|
||||
filename_lookup+0x136/0x280
|
||||
user_path_at_empty+0x47/0x60
|
||||
do_faccessat+0x11a/0x390
|
||||
__x64_sys_access+0x3c/0x50
|
||||
do_syscall_64+0x85/0x260
|
||||
entry_SYSCALL_64_after_hwframe+0x44/0xa9
|
||||
|
||||
Reported by Kernel Concurrency Sanitizer on:
|
||||
CPU: 6 PID: 166 Comm: systemd-journal Not tainted 5.3.0-rc7+ #1
|
||||
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014
|
||||
==================================================================
|
||||
|
||||
The header of the report provides a short summary of the functions involved in
|
||||
the race. It is followed by the access types and stack traces of the 2 threads
|
||||
involved in the data race.
|
||||
|
||||
The other less common type of data race report looks like this::
|
||||
|
||||
==================================================================
|
||||
BUG: KCSAN: data-race in e1000_clean_rx_irq+0x551/0xb10
|
||||
|
||||
race at unknown origin, with read to 0xffff933db8a2ae6c of 1 bytes by interrupt on cpu 0:
|
||||
e1000_clean_rx_irq+0x551/0xb10
|
||||
e1000_clean+0x533/0xda0
|
||||
net_rx_action+0x329/0x900
|
||||
__do_softirq+0xdb/0x2db
|
||||
irq_exit+0x9b/0xa0
|
||||
do_IRQ+0x9c/0xf0
|
||||
ret_from_intr+0x0/0x18
|
||||
default_idle+0x3f/0x220
|
||||
arch_cpu_idle+0x21/0x30
|
||||
do_idle+0x1df/0x230
|
||||
cpu_startup_entry+0x14/0x20
|
||||
rest_init+0xc5/0xcb
|
||||
arch_call_rest_init+0x13/0x2b
|
||||
start_kernel+0x6db/0x700
|
||||
|
||||
Reported by Kernel Concurrency Sanitizer on:
|
||||
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.3.0-rc7+ #2
|
||||
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014
|
||||
==================================================================
|
||||
|
||||
This report is generated where it was not possible to determine the other
|
||||
racing thread, but a race was inferred due to the data value of the watched
|
||||
memory location having changed. These can occur either due to missing
|
||||
instrumentation or e.g. DMA accesses. These reports will only be generated if
|
||||
``CONFIG_KCSAN_REPORT_RACE_UNKNOWN_ORIGIN=y`` (selected by default).
|
||||
|
||||
Selective analysis
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
It may be desirable to disable data race detection for specific accesses,
|
||||
functions, compilation units, or entire subsystems. For static blacklisting,
|
||||
the below options are available:
|
||||
|
||||
* KCSAN understands the ``data_race(expr)`` annotation, which tells KCSAN that
|
||||
any data races due to accesses in ``expr`` should be ignored and resulting
|
||||
behaviour when encountering a data race is deemed safe.
|
||||
|
||||
* Disabling data race detection for entire functions can be accomplished by
|
||||
using the function attribute ``__no_kcsan``::
|
||||
|
||||
__no_kcsan
|
||||
void foo(void) {
|
||||
...
|
||||
|
||||
To dynamically limit for which functions to generate reports, see the
|
||||
`DebugFS interface`_ blacklist/whitelist feature.
|
||||
|
||||
For ``__always_inline`` functions, replace ``__always_inline`` with
|
||||
``__no_kcsan_or_inline`` (which implies ``__always_inline``)::
|
||||
|
||||
static __no_kcsan_or_inline void foo(void) {
|
||||
...
|
||||
|
||||
* To disable data race detection for a particular compilation unit, add to the
|
||||
``Makefile``::
|
||||
|
||||
KCSAN_SANITIZE_file.o := n
|
||||
|
||||
* To disable data race detection for all compilation units listed in a
|
||||
``Makefile``, add to the respective ``Makefile``::
|
||||
|
||||
KCSAN_SANITIZE := n
|
||||
|
||||
Furthermore, it is possible to tell KCSAN to show or hide entire classes of
|
||||
data races, depending on preferences. These can be changed via the following
|
||||
Kconfig options:
|
||||
|
||||
* ``CONFIG_KCSAN_REPORT_VALUE_CHANGE_ONLY``: If enabled and a conflicting write
|
||||
is observed via a watchpoint, but the data value of the memory location was
|
||||
observed to remain unchanged, do not report the data race.
|
||||
|
||||
* ``CONFIG_KCSAN_ASSUME_PLAIN_WRITES_ATOMIC``: Assume that plain aligned writes
|
||||
up to word size are atomic by default. Assumes that such writes are not
|
||||
subject to unsafe compiler optimizations resulting in data races. The option
|
||||
causes KCSAN to not report data races due to conflicts where the only plain
|
||||
accesses are aligned writes up to word size.
|
||||
|
||||
DebugFS interface
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
The file ``/sys/kernel/debug/kcsan`` provides the following interface:
|
||||
|
||||
* Reading ``/sys/kernel/debug/kcsan`` returns various runtime statistics.
|
||||
|
||||
* Writing ``on`` or ``off`` to ``/sys/kernel/debug/kcsan`` allows turning KCSAN
|
||||
on or off, respectively.
|
||||
|
||||
* Writing ``!some_func_name`` to ``/sys/kernel/debug/kcsan`` adds
|
||||
``some_func_name`` to the report filter list, which (by default) blacklists
|
||||
reporting data races where either one of the top stackframes are a function
|
||||
in the list.
|
||||
|
||||
* Writing either ``blacklist`` or ``whitelist`` to ``/sys/kernel/debug/kcsan``
|
||||
changes the report filtering behaviour. For example, the blacklist feature
|
||||
can be used to silence frequently occurring data races; the whitelist feature
|
||||
can help with reproduction and testing of fixes.
|
||||
|
||||
Tuning performance
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Core parameters that affect KCSAN's overall performance and bug detection
|
||||
ability are exposed as kernel command-line arguments whose defaults can also be
|
||||
changed via the corresponding Kconfig options.
|
||||
|
||||
* ``kcsan.skip_watch`` (``CONFIG_KCSAN_SKIP_WATCH``): Number of per-CPU memory
|
||||
operations to skip, before another watchpoint is set up. Setting up
|
||||
watchpoints more frequently will result in the likelihood of races to be
|
||||
observed to increase. This parameter has the most significant impact on
|
||||
overall system performance and race detection ability.
|
||||
|
||||
* ``kcsan.udelay_task`` (``CONFIG_KCSAN_UDELAY_TASK``): For tasks, the
|
||||
microsecond delay to stall execution after a watchpoint has been set up.
|
||||
Larger values result in the window in which we may observe a race to
|
||||
increase.
|
||||
|
||||
* ``kcsan.udelay_interrupt`` (``CONFIG_KCSAN_UDELAY_INTERRUPT``): For
|
||||
interrupts, the microsecond delay to stall execution after a watchpoint has
|
||||
been set up. Interrupts have tighter latency requirements, and their delay
|
||||
should generally be smaller than the one chosen for tasks.
|
||||
|
||||
They may be tweaked at runtime via ``/sys/module/kcsan/parameters/``.
|
||||
|
||||
Data Races
|
||||
----------
|
||||
|
||||
In an execution, two memory accesses form a *data race* if they *conflict*,
|
||||
they happen concurrently in different threads, and at least one of them is a
|
||||
*plain access*; they *conflict* if both access the same memory location, and at
|
||||
least one is a write. For a more thorough discussion and definition, see `"Plain
|
||||
Accesses and Data Races" in the LKMM`_.
|
||||
|
||||
.. _"Plain Accesses and Data Races" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/memory-model/Documentation/explanation.txt#n1922
|
||||
|
||||
Relationship with the Linux-Kernel Memory Consistency Model (LKMM)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The LKMM defines the propagation and ordering rules of various memory
|
||||
operations, which gives developers the ability to reason about concurrent code.
|
||||
Ultimately this allows to determine the possible executions of concurrent code,
|
||||
and if that code is free from data races.
|
||||
|
||||
KCSAN is aware of *marked atomic operations* (``READ_ONCE``, ``WRITE_ONCE``,
|
||||
``atomic_*``, etc.), but is oblivious of any ordering guarantees and simply
|
||||
assumes that memory barriers are placed correctly. In other words, KCSAN
|
||||
assumes that as long as a plain access is not observed to race with another
|
||||
conflicting access, memory operations are correctly ordered.
|
||||
|
||||
This means that KCSAN will not report *potential* data races due to missing
|
||||
memory ordering. Developers should therefore carefully consider the required
|
||||
memory ordering requirements that remain unchecked. If, however, missing
|
||||
memory ordering (that is observable with a particular compiler and
|
||||
architecture) leads to an observable data race (e.g. entering a critical
|
||||
section erroneously), KCSAN would report the resulting data race.
|
||||
|
||||
Race Detection Beyond Data Races
|
||||
--------------------------------
|
||||
|
||||
For code with complex concurrency design, race-condition bugs may not always
|
||||
manifest as data races. Race conditions occur if concurrently executing
|
||||
operations result in unexpected system behaviour. On the other hand, data races
|
||||
are defined at the C-language level. The following macros can be used to check
|
||||
properties of concurrent code where bugs would not manifest as data races.
|
||||
|
||||
.. kernel-doc:: include/linux/kcsan-checks.h
|
||||
:functions: ASSERT_EXCLUSIVE_WRITER ASSERT_EXCLUSIVE_WRITER_SCOPED
|
||||
ASSERT_EXCLUSIVE_ACCESS ASSERT_EXCLUSIVE_ACCESS_SCOPED
|
||||
ASSERT_EXCLUSIVE_BITS
|
||||
|
||||
Implementation Details
|
||||
----------------------
|
||||
|
||||
KCSAN relies on observing that two accesses happen concurrently. Crucially, we
|
||||
want to (a) increase the chances of observing races (especially for races that
|
||||
manifest rarely), and (b) be able to actually observe them. We can accomplish
|
||||
(a) by injecting various delays, and (b) by using address watchpoints (or
|
||||
breakpoints).
|
||||
|
||||
If we deliberately stall a memory access, while we have a watchpoint for its
|
||||
address set up, and then observe the watchpoint to fire, two accesses to the
|
||||
same address just raced. Using hardware watchpoints, this is the approach taken
|
||||
in `DataCollider
|
||||
<http://usenix.org/legacy/events/osdi10/tech/full_papers/Erickson.pdf>`_.
|
||||
Unlike DataCollider, KCSAN does not use hardware watchpoints, but instead
|
||||
relies on compiler instrumentation and "soft watchpoints".
|
||||
|
||||
In KCSAN, watchpoints are implemented using an efficient encoding that stores
|
||||
access type, size, and address in a long; the benefits of using "soft
|
||||
watchpoints" are portability and greater flexibility. KCSAN then relies on the
|
||||
compiler instrumenting plain accesses. For each instrumented plain access:
|
||||
|
||||
1. Check if a matching watchpoint exists; if yes, and at least one access is a
|
||||
write, then we encountered a racing access.
|
||||
|
||||
2. Periodically, if no matching watchpoint exists, set up a watchpoint and
|
||||
stall for a small randomized delay.
|
||||
|
||||
3. Also check the data value before the delay, and re-check the data value
|
||||
after delay; if the values mismatch, we infer a race of unknown origin.
|
||||
|
||||
To detect data races between plain and marked accesses, KCSAN also annotates
|
||||
marked accesses, but only to check if a watchpoint exists; i.e. KCSAN never
|
||||
sets up a watchpoint on marked accesses. By never setting up watchpoints for
|
||||
marked operations, if all accesses to a variable that is accessed concurrently
|
||||
are properly marked, KCSAN will never trigger a watchpoint and therefore never
|
||||
report the accesses.
|
||||
|
||||
Key Properties
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
1. **Memory Overhead:** The overall memory overhead is only a few MiB
|
||||
depending on configuration. The current implementation uses a small array of
|
||||
longs to encode watchpoint information, which is negligible.
|
||||
|
||||
2. **Performance Overhead:** KCSAN's runtime aims to be minimal, using an
|
||||
efficient watchpoint encoding that does not require acquiring any shared
|
||||
locks in the fast-path. For kernel boot on a system with 8 CPUs:
|
||||
|
||||
- 5.0x slow-down with the default KCSAN config;
|
||||
- 2.8x slow-down from runtime fast-path overhead only (set very large
|
||||
``KCSAN_SKIP_WATCH`` and unset ``KCSAN_SKIP_WATCH_RANDOMIZE``).
|
||||
|
||||
3. **Annotation Overheads:** Minimal annotations are required outside the KCSAN
|
||||
runtime. As a result, maintenance overheads are minimal as the kernel
|
||||
evolves.
|
||||
|
||||
4. **Detects Racy Writes from Devices:** Due to checking data values upon
|
||||
setting up watchpoints, racy writes from devices can also be detected.
|
||||
|
||||
5. **Memory Ordering:** KCSAN is *not* explicitly aware of the LKMM's ordering
|
||||
rules; this may result in missed data races (false negatives).
|
||||
|
||||
6. **Analysis Accuracy:** For observed executions, due to using a sampling
|
||||
strategy, the analysis is *unsound* (false negatives possible), but aims to
|
||||
be complete (no false positives).
|
||||
|
||||
Alternatives Considered
|
||||
-----------------------
|
||||
|
||||
An alternative data race detection approach for the kernel can be found in the
|
||||
`Kernel Thread Sanitizer (KTSAN) <https://github.com/google/ktsan/wiki>`_.
|
||||
KTSAN is a happens-before data race detector, which explicitly establishes the
|
||||
happens-before order between memory operations, which can then be used to
|
||||
determine data races as defined in `Data Races`_.
|
||||
|
||||
To build a correct happens-before relation, KTSAN must be aware of all ordering
|
||||
rules of the LKMM and synchronization primitives. Unfortunately, any omission
|
||||
leads to large numbers of false positives, which is especially detrimental in
|
||||
the context of the kernel which includes numerous custom synchronization
|
||||
mechanisms. To track the happens-before relation, KTSAN's implementation
|
||||
requires metadata for each memory location (shadow memory), which for each page
|
||||
corresponds to 4 pages of shadow memory, and can translate into overhead of
|
||||
tens of GiB on a large system.
|
||||
@ -151,6 +151,29 @@ note some tests will require root privileges::
|
||||
$ cd kselftest
|
||||
$ ./run_kselftest.sh
|
||||
|
||||
Packaging selftests
|
||||
===================
|
||||
|
||||
In some cases packaging is desired, such as when tests need to run on a
|
||||
different system. To package selftests, run::
|
||||
|
||||
$ make -C tools/testing/selftests gen_tar
|
||||
|
||||
This generates a tarball in the `INSTALL_PATH/kselftest-packages` directory. By
|
||||
default, `.gz` format is used. The tar format can be overridden by specifying
|
||||
a `FORMAT` make variable. Any value recognized by `tar's auto-compress`_ option
|
||||
is supported, such as::
|
||||
|
||||
$ make -C tools/testing/selftests gen_tar FORMAT=.xz
|
||||
|
||||
`make gen_tar` invokes `make install` so you can use it to package a subset of
|
||||
tests by using variables specified in `Running a subset of selftests`_
|
||||
section::
|
||||
|
||||
$ make -C tools/testing/selftests gen_tar TARGETS="bpf" FORMAT=.xz
|
||||
|
||||
.. _tar's auto-compress: https://www.gnu.org/software/tar/manual/html_node/gzip.html#auto_002dcompress
|
||||
|
||||
Contributing new tests
|
||||
======================
|
||||
|
||||
|
||||
@ -32,15 +32,17 @@ test targets as well. The ``.kunitconfig`` should also contain any other config
|
||||
options required by the tests.
|
||||
|
||||
A good starting point for a ``.kunitconfig`` is the KUnit defconfig:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
cd $PATH_TO_LINUX_REPO
|
||||
cp arch/um/configs/kunit_defconfig .kunitconfig
|
||||
|
||||
You can then add any other Kconfig options you wish, e.g.:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
CONFIG_LIST_KUNIT_TEST=y
|
||||
CONFIG_LIST_KUNIT_TEST=y
|
||||
|
||||
:doc:`kunit_tool <kunit-tool>` will ensure that all config options set in
|
||||
``.kunitconfig`` are set in the kernel ``.config`` before running the tests.
|
||||
@ -54,8 +56,8 @@ using.
|
||||
other tools (such as make menuconfig) to adjust other config options.
|
||||
|
||||
|
||||
Running the tests
|
||||
-----------------
|
||||
Running the tests (KUnit Wrapper)
|
||||
---------------------------------
|
||||
|
||||
To make sure that everything is set up correctly, simply invoke the Python
|
||||
wrapper from your kernel repo:
|
||||
@ -105,8 +107,9 @@ have config options ending in ``_KUNIT_TEST``.
|
||||
KUnit and KUnit tests can be compiled as modules: in this case the tests in a
|
||||
module will be run when the module is loaded.
|
||||
|
||||
Running the tests
|
||||
-----------------
|
||||
|
||||
Running the tests (w/o KUnit Wrapper)
|
||||
-------------------------------------
|
||||
|
||||
Build and run your kernel as usual. Test output will be written to the kernel
|
||||
log in `TAP <https://testanything.org/>`_ format.
|
||||
|
||||
@ -595,7 +595,7 @@ able to run one test case per invocation.
|
||||
KUnit debugfs representation
|
||||
============================
|
||||
When kunit test suites are initialized, they create an associated directory
|
||||
in /sys/kernel/debug/kunit/<test-suite>. The directory contains one file
|
||||
in ``/sys/kernel/debug/kunit/<test-suite>``. The directory contains one file
|
||||
|
||||
- results: "cat results" displays results of each test case and the results
|
||||
of the entire suite for the last test run.
|
||||
@ -604,4 +604,4 @@ The debugfs representation is primarily of use when kunit test suites are
|
||||
run in a native environment, either as modules or builtin. Having a way
|
||||
to display results like this is valuable as otherwise results can be
|
||||
intermixed with other events in dmesg output. The maximum size of each
|
||||
results file is KUNIT_LOG_SIZE bytes (defined in include/kunit/test.h).
|
||||
results file is KUNIT_LOG_SIZE bytes (defined in ``include/kunit/test.h``).
|
||||
|
||||
@ -8,6 +8,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-apmixedsys"
|
||||
- "mediatek,mt2712-apmixedsys", "syscon"
|
||||
- "mediatek,mt6765-apmixedsys", "syscon"
|
||||
- "mediatek,mt6779-apmixedsys", "syscon"
|
||||
- "mediatek,mt6797-apmixedsys"
|
||||
- "mediatek,mt7622-apmixedsys"
|
||||
|
||||
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt6765-audsys", "syscon"
|
||||
- "mediatek,mt6779-audio", "syscon"
|
||||
- "mediatek,mt7622-audsys", "syscon"
|
||||
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
|
||||
|
||||
@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-camsys", "syscon"
|
||||
- "mediatek,mt6779-camsys", "syscon"
|
||||
- "mediatek,mt8183-camsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
@ -8,6 +8,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-imgsys", "syscon"
|
||||
- "mediatek,mt2712-imgsys", "syscon"
|
||||
- "mediatek,mt6765-imgsys", "syscon"
|
||||
- "mediatek,mt6779-imgsys", "syscon"
|
||||
- "mediatek,mt6797-imgsys", "syscon"
|
||||
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
|
||||
|
||||
@ -9,6 +9,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-infracfg", "syscon"
|
||||
- "mediatek,mt2712-infracfg", "syscon"
|
||||
- "mediatek,mt6765-infracfg", "syscon"
|
||||
- "mediatek,mt6779-infracfg_ao", "syscon"
|
||||
- "mediatek,mt6797-infracfg", "syscon"
|
||||
- "mediatek,mt7622-infracfg", "syscon"
|
||||
|
||||
@ -0,0 +1,28 @@
|
||||
Mediatek mipi0a (mipi_rx_ana_csi0a) controller
|
||||
============================
|
||||
|
||||
The Mediatek mipi0a controller provides various clocks
|
||||
to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-mipi0a", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mipi0a controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The mipi0a controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power doamins are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
||||
mipi0a: clock-controller@11c10000 {
|
||||
compatible = "mediatek,mt6765-mipi0a", "syscon";
|
||||
reg = <0 0x11c10000 0 0x1000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -9,6 +9,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt2712-mmsys", "syscon"
|
||||
- "mediatek,mt6765-mmsys", "syscon"
|
||||
- "mediatek,mt6779-mmsys", "syscon"
|
||||
- "mediatek,mt6797-mmsys", "syscon"
|
||||
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
|
||||
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt2701-pericfg
|
||||
- mediatek,mt2712-pericfg
|
||||
- mediatek,mt6765-pericfg
|
||||
- mediatek,mt7622-pericfg
|
||||
- mediatek,mt7629-pericfg
|
||||
- mediatek,mt8135-pericfg
|
||||
|
||||
@ -8,6 +8,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-topckgen"
|
||||
- "mediatek,mt2712-topckgen", "syscon"
|
||||
- "mediatek,mt6765-topckgen", "syscon"
|
||||
- "mediatek,mt6779-topckgen", "syscon"
|
||||
- "mediatek,mt6797-topckgen"
|
||||
- "mediatek,mt7622-topckgen"
|
||||
|
||||
@ -0,0 +1,27 @@
|
||||
Mediatek vcodecsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vcodecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-vcodecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vcodecsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The vcodecsys controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power doamins are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
||||
venc_gcon: clock-controller@17000000 {
|
||||
compatible = "mediatek,mt6765-vcodecsys", "syscon";
|
||||
reg = <0 0x17000000 0 0x10000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -85,9 +85,8 @@ properties:
|
||||
CPU power good signal from external PMIC to PMC is enabled.
|
||||
|
||||
nvidia,suspend-mode:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
description:
|
||||
The suspend mode that the platform should use.
|
||||
Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
|
||||
|
||||
@ -40,28 +40,25 @@ properties:
|
||||
|
||||
calxeda,led-order:
|
||||
description: Maps port numbers to offsets within the SGPIO bitstream.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 1
|
||||
maxItems: 8
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
calxeda,port-phys:
|
||||
description: |
|
||||
phandle-combophy and lane assignment, which maps each SATA port to a
|
||||
combophy and a lane within that combophy
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
- minItems: 1
|
||||
maxItems: 8
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
calxeda,tx-atten:
|
||||
description: |
|
||||
Contains TX attenuation override codes, one per port.
|
||||
The upper 24 bits of each entry are always 0 and thus ignored.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 1
|
||||
maxItems: 8
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
calxeda,sgpio-gpio:
|
||||
description: |
|
||||
|
||||
@ -71,8 +71,8 @@ examples:
|
||||
|
||||
bus@1f059000 {
|
||||
compatible = "baikal,bt1-apb", "simple-bus";
|
||||
reg = <0 0x1f059000 0 0x1000>,
|
||||
<0 0x1d000000 0 0x2040000>;
|
||||
reg = <0x1f059000 0x1000>,
|
||||
<0x1d000000 0x2040000>;
|
||||
reg-names = "ehb", "nodev";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
@ -85,8 +85,8 @@ examples:
|
||||
|
||||
bus@1f05a000 {
|
||||
compatible = "baikal,bt1-axi", "simple-bus";
|
||||
reg = <0 0x1f05a000 0 0x1000>,
|
||||
<0 0x1f04d110 0 0x8>;
|
||||
reg = <0x1f05a000 0x1000>,
|
||||
<0x1f04d110 0x8>;
|
||||
reg-names = "qos", "ehb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
188
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
Normal file
188
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
Normal file
@ -0,0 +1,188 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 Clock Control Unit Dividers
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
|
||||
responsible for the chip subsystems clocking and resetting. The CCU is
|
||||
connected with an external fixed rate oscillator, which signal is transformed
|
||||
into clocks of various frequencies and then propagated to either individual
|
||||
IP-blocks or to groups of blocks (clock domains). The transformation is done
|
||||
by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
|
||||
later ones are described in this binding. Each clock domain can be also
|
||||
individually reset by using the domain clocks divider configuration
|
||||
registers. Baikal-T1 CCU is logically divided into the next components:
|
||||
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
|
||||
in general can provide any frequency supported by the CCU PLLs).
|
||||
2) PLLs clocks generators (PLLs).
|
||||
3) AXI-bus clock dividers (AXI) - described in this binding file.
|
||||
4) System devices reference clock dividers (SYS) - described in this binding
|
||||
file.
|
||||
which are connected with each other as shown on the next figure:
|
||||
|
||||
+---------------+
|
||||
| Baikal-T1 CCU |
|
||||
| +----+------|- MIPS P5600 cores
|
||||
| +-|PLLs|------|- DDR controller
|
||||
| | +----+ |
|
||||
+----+ | | | | |
|
||||
|XTAL|--|-+ | | +---+-|
|
||||
+----+ | | | +-|AXI|-|- AXI-bus
|
||||
| | | +---+-|
|
||||
| | | |
|
||||
| | +----+---+-|- APB-bus
|
||||
| +-------|SYS|-|- Low-speed Devices
|
||||
| +---+-|- High-speed Devices
|
||||
+---------------+
|
||||
|
||||
Each sub-block is represented as a separate DT node and has an individual
|
||||
driver to be bound with.
|
||||
|
||||
In order to create signals of wide range frequencies the external oscillator
|
||||
output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
|
||||
then passed over CCU dividers to create signals required for the target clock
|
||||
domain (like AXI-bus or System Device consumers). The dividers have the
|
||||
following structure:
|
||||
|
||||
+--------------+
|
||||
CLKIN --|->+----+ 1|\ |
|
||||
SETCLK--|--|/DIV|->| | |
|
||||
CLKDIV--|--| | | |-|->CLKLOUT
|
||||
LOCK----|--+----+ | | |
|
||||
| |/ |
|
||||
| | |
|
||||
EN------|-----------+ |
|
||||
RST-----|--------------|->RSTOUT
|
||||
+--------------+
|
||||
|
||||
where CLKIN is the reference clock coming either from CCU PLLs or from an
|
||||
external clock oscillator, SETCLK - a command to update the output clock in
|
||||
accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
|
||||
the output clock stabilization, EN - enable/disable the divider block,
|
||||
RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
|
||||
peculiarities the dividers may lack of some functionality depicted on the
|
||||
figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
|
||||
clock provider just doesn't expose either switching functions, or the rate
|
||||
configuration, or both of them.
|
||||
|
||||
The clock dividers, which output clock is then consumed by the SoC individual
|
||||
devices, are united into a single clocks provider called System Devices CCU.
|
||||
Similarly the dividers with output clocks utilized as AXI-bus reference clocks
|
||||
are called AXI-bus CCU. Both of them use the common clock bindings with no
|
||||
custom properties. The list of exported clocks and reset signals can be found
|
||||
in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
|
||||
'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
|
||||
are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
|
||||
to be a children of later one.
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: baikal,bt1-ccu-axi
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: CCU SATA PLL output clock
|
||||
- description: CCU PCIe PLL output clock
|
||||
- description: CCU Ethernet PLL output clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sata_clk
|
||||
- const: pcie_clk
|
||||
- const: eth_clk
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock
|
||||
- description: CCU SATA PLL output clock
|
||||
- description: CCU PCIe PLL output clock
|
||||
- description: CCU Ethernet PLL output clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref_clk
|
||||
- const: sata_clk
|
||||
- const: pcie_clk
|
||||
- const: eth_clk
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- baikal,bt1-ccu-axi
|
||||
- baikal,bt1-ccu-sys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# AXI-bus Clock Control Unit node:
|
||||
- |
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
|
||||
clock-controller@1f04d030 {
|
||||
compatible = "baikal,bt1-ccu-axi";
|
||||
reg = <0x1f04d030 0x030>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
clocks = <&ccu_pll CCU_SATA_PLL>,
|
||||
<&ccu_pll CCU_PCIE_PLL>,
|
||||
<&ccu_pll CCU_ETH_PLL>;
|
||||
clock-names = "sata_clk", "pcie_clk", "eth_clk";
|
||||
};
|
||||
# System Devices Clock Control Unit node:
|
||||
- |
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
|
||||
clock-controller@1f04d060 {
|
||||
compatible = "baikal,bt1-ccu-sys";
|
||||
reg = <0x1f04d060 0x0a0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>,
|
||||
<&ccu_pll CCU_SATA_PLL>,
|
||||
<&ccu_pll CCU_PCIE_PLL>,
|
||||
<&ccu_pll CCU_ETH_PLL>;
|
||||
clock-names = "ref_clk", "sata_clk", "pcie_clk",
|
||||
"eth_clk";
|
||||
};
|
||||
# Required Clock Control Unit PLL node:
|
||||
- |
|
||||
ccu_pll: clock-controller@1f04d000 {
|
||||
compatible = "baikal,bt1-ccu-pll";
|
||||
reg = <0x1f04d000 0x028>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>;
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
...
|
||||
131
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
Normal file
131
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
Normal file
@ -0,0 +1,131 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 Clock Control Unit PLL
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
|
||||
responsible for the chip subsystems clocking and resetting. The CCU is
|
||||
connected with an external fixed rate oscillator, which signal is transformed
|
||||
into clocks of various frequencies and then propagated to either individual
|
||||
IP-blocks or to groups of blocks (clock domains). The transformation is done
|
||||
by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
|
||||
It's logically divided into the next components:
|
||||
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
|
||||
in general can provide any frequency supported by the CCU PLLs).
|
||||
2) PLLs clocks generators (PLLs) - described in this binding file.
|
||||
3) AXI-bus clock dividers (AXI).
|
||||
4) System devices reference clock dividers (SYS).
|
||||
which are connected with each other as shown on the next figure:
|
||||
|
||||
+---------------+
|
||||
| Baikal-T1 CCU |
|
||||
| +----+------|- MIPS P5600 cores
|
||||
| +-|PLLs|------|- DDR controller
|
||||
| | +----+ |
|
||||
+----+ | | | | |
|
||||
|XTAL|--|-+ | | +---+-|
|
||||
+----+ | | | +-|AXI|-|- AXI-bus
|
||||
| | | +---+-|
|
||||
| | | |
|
||||
| | +----+---+-|- APB-bus
|
||||
| +-------|SYS|-|- Low-speed Devices
|
||||
| +---+-|- High-speed Devices
|
||||
+---------------+
|
||||
|
||||
Each CCU sub-block is represented as a separate dts-node and has an
|
||||
individual driver to be bound with.
|
||||
|
||||
In order to create signals of wide range frequencies the external oscillator
|
||||
output is primarily connected to a set of CCU PLLs. There are five PLLs
|
||||
to create a clock for the MIPS P5600 cores, the embedded DDR controller,
|
||||
SATA, Ethernet and PCIe domains. The last three domains though named by the
|
||||
biggest system interfaces in fact include nearly all of the rest SoC
|
||||
peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
|
||||
with an interface wrapper (so called safe PLL' clocks switcher) to simplify
|
||||
the PLL configuration procedure. The PLLs work as depicted on the next
|
||||
diagram:
|
||||
|
||||
+--------------------------+
|
||||
| |
|
||||
+-->+---+ +---+ +---+ | +---+ 0|\
|
||||
CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
|
||||
+---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
|
||||
CLKOD---------C----------------+ 1| |
|
||||
+--------C--------------------------->|/
|
||||
| | ^
|
||||
Rclk-+->+---+ | |
|
||||
CLKR--->|/NR|-+ |
|
||||
+---+ |
|
||||
BYPASS--------------------------------------+
|
||||
BWADJ--->
|
||||
|
||||
where Rclk is the reference clock coming from XTAL, NR - reference clock
|
||||
divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
|
||||
output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
|
||||
the binding supports the PLL dividers configuration in accordance with a
|
||||
requested rate, while bypassing and bandwidth adjustment settings can be
|
||||
added in future if it gets to be necessary.
|
||||
|
||||
The PLLs CLKOUT is then either directly connected with the corresponding
|
||||
clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
|
||||
divider to create a signal required for the clock domain.
|
||||
|
||||
The CCU PLL dts-node uses the common clock bindings with no custom
|
||||
parameters. The list of exported clocks can be found in
|
||||
'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
|
||||
Baikal-T1 SoC System Controller its DT node is supposed to be a child of
|
||||
later one.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: baikal,bt1-ccu-pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
description: External reference clock
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ref_clk
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# Clock Control Unit PLL node:
|
||||
- |
|
||||
clock-controller@1f04d000 {
|
||||
compatible = "baikal,bt1-ccu-pll";
|
||||
reg = <0x1f04d000 0x028>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>;
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
# Required external oscillator:
|
||||
- |
|
||||
clk25m: clock-oscillator-25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "clk25m";
|
||||
};
|
||||
...
|
||||
@ -12,6 +12,7 @@ Required properties:
|
||||
"idt,5p49v5933"
|
||||
"idt,5p49v5935"
|
||||
"idt,5p49v6901"
|
||||
"idt,5p49v6965"
|
||||
- reg: i2c device address, shall be 0x68 or 0x6a.
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
|
||||
@ -23,7 +23,6 @@ properties:
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
maxItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -23,7 +23,6 @@ properties:
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
maxItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -23,7 +23,6 @@ properties:
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
maxItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -23,7 +23,6 @@ properties:
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
maxItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -23,7 +23,6 @@ properties:
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
maxItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
46
Documentation/devicetree/bindings/clock/intel,agilex.yaml
Normal file
46
Documentation/devicetree/bindings/clock/intel,agilex.yaml
Normal file
@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA Agilex platform clock controller binding
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
description:
|
||||
The Intel Agilex Clock controller is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,agilex-clkmgr
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node:
|
||||
- |
|
||||
clkmgr: clock-controller@ffd10000 {
|
||||
compatible = "intel,agilex-clkmgr";
|
||||
reg = <0xffd10000 0x1000>;
|
||||
clocks = <&osc1>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
44
Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
Normal file
44
Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
Normal file
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rahul.tanwar@linux.intel.com>
|
||||
|
||||
description: |
|
||||
Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
|
||||
all means to access the CGU hardware module in order to generate a series
|
||||
of clocks for the whole system and individual peripherals.
|
||||
|
||||
Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
|
||||
defines all available clocks as macros. These macros can be used in device
|
||||
tree sources.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,cgu-lgm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
cgu: clock-controller@e0200000 {
|
||||
compatible = "intel,cgu-lgm";
|
||||
reg = <0xe0200000 0x33c>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell MMP2 Audio Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Lubomir Rintel <lkundrak@v3.sk>
|
||||
|
||||
description: |
|
||||
The audio clock controller generates and supplies the clocks to the audio
|
||||
codec.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifiers could be found in
|
||||
<dt-bindings/clock/marvell,mmp2-audio.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,mmp2-audio-clock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Audio subsystem clock
|
||||
- description: The crystal oscillator clock
|
||||
- description: First I2S clock
|
||||
- description: Second I2S clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: audio
|
||||
- const: vctcxo
|
||||
- const: i2s0
|
||||
- const: i2s1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/marvell,mmp2-audio.h>
|
||||
#include <dt-bindings/clock/marvell,mmp2.h>
|
||||
#include <dt-bindings/power/marvell,mmp2.h>
|
||||
|
||||
clock-controller@d42a0c30 {
|
||||
compatible = "marvell,mmp2-audio-clock";
|
||||
reg = <0xd42a0c30 0x10>;
|
||||
clock-names = "audio", "vctcxo", "i2s0", "i2s1";
|
||||
clocks = <&soc_clocks MMP2_CLK_AUDIO>,
|
||||
<&soc_clocks MMP2_CLK_VCTCXO>,
|
||||
<&soc_clocks MMP2_CLK_I2S0>,
|
||||
<&soc_clocks MMP2_CLK_I2S1>;
|
||||
power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -42,12 +42,16 @@ properties:
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -61,4 +65,5 @@ examples:
|
||||
reg-names = "mpmu", "apmu", "apbc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
@ -1,22 +0,0 @@
|
||||
Qualcomm MSM8916 A53 PLL Binding
|
||||
--------------------------------
|
||||
The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies
|
||||
above 1GHz.
|
||||
|
||||
Required properties :
|
||||
- compatible : Shall contain only one of the following:
|
||||
|
||||
"qcom,msm8916-a53pll"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
|
||||
- #clock-cells : must be set to <0>
|
||||
|
||||
Example:
|
||||
|
||||
a53pll: clock@b016000 {
|
||||
compatible = "qcom,msm8916-a53pll";
|
||||
reg = <0xb016000 0x40>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
40
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
Normal file
40
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
Normal file
@ -0,0 +1,40 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm A53 PLL Binding
|
||||
|
||||
maintainers:
|
||||
- Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
||||
|
||||
description:
|
||||
The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
|
||||
frequencies above 1GHz.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm8916-a53pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
#Example 1 - A53 PLL found on MSM8916 devices
|
||||
- |
|
||||
a53pll: clock@b016000 {
|
||||
compatible = "qcom,msm8916-a53pll";
|
||||
reg = <0xb016000 0x40>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
@ -22,6 +22,8 @@ description: |
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h
|
||||
@ -41,6 +43,7 @@ properties:
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
|
||||
@ -67,6 +67,10 @@ properties:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding
|
||||
|
||||
vdd-gfx-supply:
|
||||
description:
|
||||
Regulator supply for the GPU_GX GDSC
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas CPG DIV6 Clock
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
|
||||
Generator (CPG). Their clock input is divided by a configurable factor from 1
|
||||
to 64.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a73a4-div6-clock # R-Mobile APE6
|
||||
- renesas,r8a7740-div6-clock # R-Mobile A1
|
||||
- renesas,sh73a0-div6-clock # SH-Mobile AG5
|
||||
- const: renesas,cpg-div6-clock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
oneOf:
|
||||
- maxItems: 1
|
||||
- maxItems: 4
|
||||
- maxItems: 8
|
||||
description:
|
||||
For clocks with multiple parents, invalid settings must be specified as
|
||||
"<0>".
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
clock-output-names: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a73a4-clock.h>
|
||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615007c 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
|
||||
<&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
@ -1,40 +0,0 @@
|
||||
* Renesas CPG DIV6 Clock
|
||||
|
||||
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
|
||||
Generator (CPG). Their clock input is divided by a configurable factor from 1
|
||||
to 64.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
|
||||
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
|
||||
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
|
||||
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
|
||||
- "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
|
||||
- "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
|
||||
- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
|
||||
and "renesas,cpg-div6-clock" as a fallback.
|
||||
- reg: Base address and length of the memory resource used by the DIV6 clock
|
||||
- clocks: Reference to the parent clock(s); either one, four, or eight
|
||||
clocks must be specified. For clocks with multiple parents, invalid
|
||||
settings must be specified as "<0>".
|
||||
- #clock-cells: Must be 0
|
||||
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- clock-output-names: The name of the clock as a free-form string
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615007c 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi2ck";
|
||||
};
|
||||
@ -25,6 +25,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r7s9210-cpg-mssr # RZ/A2
|
||||
- renesas,r8a7742-cpg-mssr # RZ/G1H
|
||||
- renesas,r8a7743-cpg-mssr # RZ/G1M
|
||||
- renesas,r8a7744-cpg-mssr # RZ/G1N
|
||||
- renesas,r8a7745-cpg-mssr # RZ/G1E
|
||||
|
||||
@ -1,60 +0,0 @@
|
||||
* Renesas CPG Module Stop (MSTP) Clocks
|
||||
|
||||
The CPG can gate SoC device clocks. The gates are organized in groups of up to
|
||||
32 gates.
|
||||
|
||||
This device tree binding describes a single 32 gate clocks group per node.
|
||||
Clocks are referenced by user nodes by the MSTP node phandle and the clock
|
||||
index in the group, from 0 to 31.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
|
||||
- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
|
||||
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
|
||||
- "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
|
||||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
|
||||
- "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
|
||||
- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
|
||||
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
|
||||
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
|
||||
and "renesas,cpg-mstp-clocks" as a fallback.
|
||||
- reg: Base address and length of the I/O mapped registers used by the MSTP
|
||||
clocks. The first register is the clock control register and is mandatory.
|
||||
The second register is the clock status register and is optional when not
|
||||
implemented in hardware.
|
||||
- clocks: Reference to the parent clocks, one per output clock. The parents
|
||||
must appear in the same order as the output clocks.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The name of the clocks as free-form strings
|
||||
- clock-indices: Indices of the gate clocks into the group (0 to 31)
|
||||
|
||||
The clocks, clock-output-names and clock-indices properties contain one entry
|
||||
per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
|
||||
clocks must not be declared.
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
#include <dt-bindings/clock/r8a7790-clock.h>
|
||||
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
|
||||
<&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
|
||||
<&mmc0_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names =
|
||||
"tpu0", "mmcif1", "sdhi3", "sdhi2",
|
||||
"sdhi1", "sdhi0", "mmcif0";
|
||||
clock-indices = <
|
||||
R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
|
||||
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
|
||||
R8A7790_CLK_MMCIF0
|
||||
>;
|
||||
};
|
||||
@ -0,0 +1,82 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
|
||||
organized in groups of up to 32 gates.
|
||||
|
||||
This device tree binding describes a single 32 gate clocks group per node.
|
||||
Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
|
||||
and the clock index in the group, from 0 to 31.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r7s72100-mstp-clocks # RZ/A1
|
||||
- renesas,r8a73a4-mstp-clocks # R-Mobile APE6
|
||||
- renesas,r8a7740-mstp-clocks # R-Mobile A1
|
||||
- renesas,r8a7778-mstp-clocks # R-Car M1
|
||||
- renesas,r8a7779-mstp-clocks # R-Car H1
|
||||
- renesas,sh73a0-mstp-clocks # SH-Mobile AG5
|
||||
- const: renesas,cpg-mstp-clocks
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Module Stop Control Register (MSTPCR)
|
||||
- description: Module Stop Status Register (MSTPSR)
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clock-indices:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- clock-indices
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a73a4-clock.h>
|
||||
mstp2_clks: mstp2_clks@e6150138 {
|
||||
compatible = "renesas,r8a73a4-mstp-clocks",
|
||||
"renesas,cpg-mstp-clocks";
|
||||
reg = <0xe6150138 4>, <0xe6150040 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
|
||||
R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
|
||||
R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
|
||||
R8A73A4_CLK_DMAC
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
|
||||
"dmac";
|
||||
};
|
||||
@ -27,7 +27,9 @@ Required properties:
|
||||
- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
|
||||
an R8A7795 SoC.
|
||||
"renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
|
||||
an R8A7796 SoC.
|
||||
an R8A77960 SoC.
|
||||
"renesas,r8a77961-rcar-usb2-clock-sel" if the device if a part of
|
||||
an R8A77961 SoC.
|
||||
"renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
|
||||
compatible device.
|
||||
|
||||
|
||||
@ -1,15 +1,21 @@
|
||||
Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator.
|
||||
Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
|
||||
i2c clock generator.
|
||||
|
||||
Reference
|
||||
[1] Si5341 Data Sheet
|
||||
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
|
||||
[2] Si5341 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
|
||||
[3] Si5345 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
|
||||
|
||||
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
|
||||
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
|
||||
in turn can be directed to any of the 10 (or 4) outputs through a divider.
|
||||
The internal structure of the clock generators can be found in [2].
|
||||
The Si5345 is similar to the Si5341 with the addition of fractional input
|
||||
dividers and automatic input selection, as described in [3].
|
||||
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
|
||||
|
||||
The driver can be used in "as is" mode, reading the current settings from the
|
||||
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
|
||||
@ -28,6 +34,9 @@ Required properties:
|
||||
- compatible: shall be one of the following:
|
||||
"silabs,si5340" - Si5340 A/B/C/D
|
||||
"silabs,si5341" - Si5341 A/B/C/D
|
||||
"silabs,si5342" - Si5342 A/B/C/D
|
||||
"silabs,si5344" - Si5344 A/B/C/D
|
||||
"silabs,si5345" - Si5345 A/B/C/D
|
||||
- reg: i2c device address, usually 0x74
|
||||
- #clock-cells: from common clock binding; shall be set to 2.
|
||||
The first value is "0" for outputs, "1" for synthesizers.
|
||||
|
||||
@ -28,6 +28,7 @@ properties:
|
||||
- sprd,sc9863a-rpll
|
||||
- sprd,sc9863a-dpll
|
||||
- sprd,sc9863a-mm-gate
|
||||
- sprd,sc9863a-mm-clk
|
||||
- sprd,sc9863a-apapb-gate
|
||||
|
||||
clocks:
|
||||
|
||||
@ -106,8 +106,8 @@ examples:
|
||||
#include <dt-bindings/power/rk3288-power.h>
|
||||
vopb: vopb@ff930000 {
|
||||
compatible = "rockchip,rk3288-vop";
|
||||
reg = <0x0 0xff930000 0x0 0x19c>,
|
||||
<0x0 0xff931000 0x0 0x1000>;
|
||||
reg = <0xff930000 0x19c>,
|
||||
<0xff931000 0x1000>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_VOP0>,
|
||||
<&cru DCLK_VOP0>,
|
||||
|
||||
@ -1,117 +0,0 @@
|
||||
* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
|
||||
|
||||
Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA
|
||||
controller instances named DMAC capable of serving multiple clients. Channels
|
||||
can be dedicated to specific clients or shared between a large number of
|
||||
clients.
|
||||
|
||||
Each DMA client is connected to one dedicated port of the DMAC, identified by
|
||||
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
|
||||
256 clients in total. When the number of hardware channels is lower than the
|
||||
number of clients to be served, channels must be shared between multiple DMA
|
||||
clients. The association of DMA clients to DMAC channels is fully dynamic and
|
||||
not described in these device tree bindings.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,dmac-r8a7743" (RZ/G1M)
|
||||
- "renesas,dmac-r8a7744" (RZ/G1N)
|
||||
- "renesas,dmac-r8a7745" (RZ/G1E)
|
||||
- "renesas,dmac-r8a77470" (RZ/G1C)
|
||||
- "renesas,dmac-r8a774a1" (RZ/G2M)
|
||||
- "renesas,dmac-r8a774b1" (RZ/G2N)
|
||||
- "renesas,dmac-r8a774c0" (RZ/G2E)
|
||||
- "renesas,dmac-r8a7790" (R-Car H2)
|
||||
- "renesas,dmac-r8a7791" (R-Car M2-W)
|
||||
- "renesas,dmac-r8a7792" (R-Car V2H)
|
||||
- "renesas,dmac-r8a7793" (R-Car M2-N)
|
||||
- "renesas,dmac-r8a7794" (R-Car E2)
|
||||
- "renesas,dmac-r8a7795" (R-Car H3)
|
||||
- "renesas,dmac-r8a7796" (R-Car M3-W)
|
||||
- "renesas,dmac-r8a77961" (R-Car M3-W+)
|
||||
- "renesas,dmac-r8a77965" (R-Car M3-N)
|
||||
- "renesas,dmac-r8a77970" (R-Car V3M)
|
||||
- "renesas,dmac-r8a77980" (R-Car V3H)
|
||||
- "renesas,dmac-r8a77990" (R-Car E3)
|
||||
- "renesas,dmac-r8a77995" (R-Car D3)
|
||||
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
|
||||
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
||||
interrupt-names.
|
||||
- interrupt-names: one entry for the error interrupt, named "error", plus one
|
||||
entry per channel, named "ch%u", where %u is the channel number ranging from
|
||||
zero to the number of channels minus one.
|
||||
|
||||
- clock-names: "fck" for the functional clock
|
||||
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
||||
in clock-names.
|
||||
- clock-names: must contain "fck" for the functional clock.
|
||||
|
||||
- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
|
||||
connected to the DMA client
|
||||
- dma-channels: number of DMA channels
|
||||
|
||||
Example: R8A7790 (R-Car H2) SYS-DMACs
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x20000>;
|
||||
interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
|
||||
0 200 IRQ_TYPE_LEVEL_HIGH
|
||||
0 201 IRQ_TYPE_LEVEL_HIGH
|
||||
0 202 IRQ_TYPE_LEVEL_HIGH
|
||||
0 203 IRQ_TYPE_LEVEL_HIGH
|
||||
0 204 IRQ_TYPE_LEVEL_HIGH
|
||||
0 205 IRQ_TYPE_LEVEL_HIGH
|
||||
0 206 IRQ_TYPE_LEVEL_HIGH
|
||||
0 207 IRQ_TYPE_LEVEL_HIGH
|
||||
0 208 IRQ_TYPE_LEVEL_HIGH
|
||||
0 209 IRQ_TYPE_LEVEL_HIGH
|
||||
0 210 IRQ_TYPE_LEVEL_HIGH
|
||||
0 211 IRQ_TYPE_LEVEL_HIGH
|
||||
0 212 IRQ_TYPE_LEVEL_HIGH
|
||||
0 213 IRQ_TYPE_LEVEL_HIGH
|
||||
0 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e6720000 {
|
||||
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
|
||||
reg = <0 0xe6720000 0 0x20000>;
|
||||
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
|
||||
0 216 IRQ_TYPE_LEVEL_HIGH
|
||||
0 217 IRQ_TYPE_LEVEL_HIGH
|
||||
0 218 IRQ_TYPE_LEVEL_HIGH
|
||||
0 219 IRQ_TYPE_LEVEL_HIGH
|
||||
0 308 IRQ_TYPE_LEVEL_HIGH
|
||||
0 309 IRQ_TYPE_LEVEL_HIGH
|
||||
0 310 IRQ_TYPE_LEVEL_HIGH
|
||||
0 311 IRQ_TYPE_LEVEL_HIGH
|
||||
0 312 IRQ_TYPE_LEVEL_HIGH
|
||||
0 313 IRQ_TYPE_LEVEL_HIGH
|
||||
0 314 IRQ_TYPE_LEVEL_HIGH
|
||||
0 315 IRQ_TYPE_LEVEL_HIGH
|
||||
0 316 IRQ_TYPE_LEVEL_HIGH
|
||||
0 317 IRQ_TYPE_LEVEL_HIGH
|
||||
0 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
150
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
Normal file
150
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
Normal file
@ -0,0 +1,150 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car and RZ/G DMA Controller
|
||||
|
||||
maintainers:
|
||||
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,dmac-r8a7743 # RZ/G1M
|
||||
- renesas,dmac-r8a7744 # RZ/G1N
|
||||
- renesas,dmac-r8a7745 # RZ/G1E
|
||||
- renesas,dmac-r8a77470 # RZ/G1C
|
||||
- renesas,dmac-r8a774a1 # RZ/G2M
|
||||
- renesas,dmac-r8a774b1 # RZ/G2N
|
||||
- renesas,dmac-r8a774c0 # RZ/G2E
|
||||
- renesas,dmac-r8a7790 # R-Car H2
|
||||
- renesas,dmac-r8a7791 # R-Car M2-W
|
||||
- renesas,dmac-r8a7792 # R-Car V2H
|
||||
- renesas,dmac-r8a7793 # R-Car M2-N
|
||||
- renesas,dmac-r8a7794 # R-Car E2
|
||||
- renesas,dmac-r8a7795 # R-Car H3
|
||||
- renesas,dmac-r8a7796 # R-Car M3-W
|
||||
- renesas,dmac-r8a77961 # R-Car M3-W+
|
||||
- renesas,dmac-r8a77965 # R-Car M3-N
|
||||
- renesas,dmac-r8a77970 # R-Car V3M
|
||||
- renesas,dmac-r8a77980 # R-Car V3H
|
||||
- renesas,dmac-r8a77990 # R-Car E3
|
||||
- renesas,dmac-r8a77995 # R-Car D3
|
||||
- const: renesas,rcar-dmac
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 9
|
||||
maxItems: 17
|
||||
|
||||
interrupt-names:
|
||||
minItems: 9
|
||||
maxItems: 17
|
||||
items:
|
||||
- const: error
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
items:
|
||||
- const: fck
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
description:
|
||||
The cell specifies the MID/RID of the DMAC port connected to
|
||||
the DMA client.
|
||||
|
||||
dma-channels:
|
||||
minimum: 8
|
||||
maximum: 16
|
||||
|
||||
dma-channel-mask: true
|
||||
|
||||
iommus:
|
||||
minItems: 8
|
||||
maxItems: 16
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#dma-cells'
|
||||
- dma-channels
|
||||
- power-domains
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
|
||||
reg = <0xe6700000 0x20000>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -1,55 +0,0 @@
|
||||
* Renesas USB DMA Controller Device Tree bindings
|
||||
|
||||
Required Properties:
|
||||
-compatible: "renesas,<soctype>-usb-dmac", "renesas,usb-dmac" as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,r8a7743-usb-dmac" (RZ/G1M)
|
||||
- "renesas,r8a7744-usb-dmac" (RZ/G1N)
|
||||
- "renesas,r8a7745-usb-dmac" (RZ/G1E)
|
||||
- "renesas,r8a77470-usb-dmac" (RZ/G1C)
|
||||
- "renesas,r8a774a1-usb-dmac" (RZ/G2M)
|
||||
- "renesas,r8a774b1-usb-dmac" (RZ/G2N)
|
||||
- "renesas,r8a774c0-usb-dmac" (RZ/G2E)
|
||||
- "renesas,r8a7790-usb-dmac" (R-Car H2)
|
||||
- "renesas,r8a7791-usb-dmac" (R-Car M2-W)
|
||||
- "renesas,r8a7793-usb-dmac" (R-Car M2-N)
|
||||
- "renesas,r8a7794-usb-dmac" (R-Car E2)
|
||||
- "renesas,r8a7795-usb-dmac" (R-Car H3)
|
||||
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
|
||||
- "renesas,r8a77961-usb-dmac" (R-Car M3-W+)
|
||||
- "renesas,r8a77965-usb-dmac" (R-Car M3-N)
|
||||
- "renesas,r8a77990-usb-dmac" (R-Car E3)
|
||||
- "renesas,r8a77995-usb-dmac" (R-Car D3)
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
||||
interrupt-names.
|
||||
- interrupt-names: one entry per channel, named "ch%u", where %u is the
|
||||
channel number ranging from zero to the number of channels minus one.
|
||||
- clocks: a list of phandle + clock-specifier pairs.
|
||||
- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC
|
||||
port connected to the DMA client.
|
||||
- dma-channels: number of DMA channels
|
||||
|
||||
Example: R8A7790 (R-Car H2) USB-DMACs
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
|
||||
reg = <0 0xe65a0000 0 0x100>;
|
||||
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
|
||||
0 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac1: dma-controller@e65b0000 {
|
||||
compatible = "renesas,usb-dmac";
|
||||
reg = <0 0xe65b0000 0 0x100>;
|
||||
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
|
||||
0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
102
Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml
Normal file
102
Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml
Normal file
@ -0,0 +1,102 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas USB DMA Controller
|
||||
|
||||
maintainers:
|
||||
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a7743-usb-dmac # RZ/G1M
|
||||
- renesas,r8a7744-usb-dmac # RZ/G1N
|
||||
- renesas,r8a7745-usb-dmac # RZ/G1E
|
||||
- renesas,r8a77470-usb-dmac # RZ/G1C
|
||||
- renesas,r8a774a1-usb-dmac # RZ/G2M
|
||||
- renesas,r8a774b1-usb-dmac # RZ/G2N
|
||||
- renesas,r8a774c0-usb-dmac # RZ/G2E
|
||||
- renesas,r8a7790-usb-dmac # R-Car H2
|
||||
- renesas,r8a7791-usb-dmac # R-Car M2-W
|
||||
- renesas,r8a7793-usb-dmac # R-Car M2-N
|
||||
- renesas,r8a7794-usb-dmac # R-Car E2
|
||||
- renesas,r8a7795-usb-dmac # R-Car H3
|
||||
- renesas,r8a7796-usb-dmac # R-Car M3-W
|
||||
- renesas,r8a77961-usb-dmac # R-Car M3-W+
|
||||
- renesas,r8a77965-usb-dmac # R-Car M3-N
|
||||
- renesas,r8a77990-usb-dmac # R-Car E3
|
||||
- renesas,r8a77995-usb-dmac # R-Car D3
|
||||
- const: renesas,usb-dmac
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- pattern: ch0
|
||||
- pattern: ch1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
description:
|
||||
The cell specifies the channel number of the DMAC port connected to
|
||||
the DMA client.
|
||||
|
||||
dma-channels:
|
||||
const: 2
|
||||
|
||||
iommus:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- '#dma-cells'
|
||||
- dma-channels
|
||||
- power-domains
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
|
||||
reg = <0xe65a0000 0x100>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 330>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 330>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -36,6 +36,11 @@ description: |
|
||||
0x1: 1/2 full FIFO
|
||||
0x2: 3/4 full FIFO
|
||||
0x3: full FIFO
|
||||
-bit 2: DMA direct mode
|
||||
0x0: FIFO mode with threshold selectable with bit 0-1
|
||||
0x1: Direct mode: each DMA request immediately initiates a transfer
|
||||
from/to the memory, FIFO is bypassed.
|
||||
|
||||
|
||||
maintainers:
|
||||
- Amelie Delaunay <amelie.delaunay@st.com>
|
||||
|
||||
@ -63,11 +63,10 @@ patternProperties:
|
||||
|
||||
snps,nr-gpios:
|
||||
description: The number of GPIO pins exported by the port.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 32
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 1
|
||||
maximum: 32
|
||||
minimum: 1
|
||||
maximum: 32
|
||||
|
||||
interrupts:
|
||||
description: |
|
||||
|
||||
@ -1,73 +0,0 @@
|
||||
* Synopsys DesignWare I2C
|
||||
|
||||
Required properties :
|
||||
|
||||
- compatible : should be "snps,designware-i2c"
|
||||
or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : <IRQ> where IRQ is the interrupt number.
|
||||
- clocks : phandles for the clocks, see the description of clock-names below.
|
||||
The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
|
||||
clock is optional. If a single clock is specified but no clock-name, it is
|
||||
the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
|
||||
|
||||
Recommended properties :
|
||||
|
||||
- clock-frequency : desired I2C bus clock frequency in Hz.
|
||||
|
||||
Optional properties :
|
||||
|
||||
- clock-names : Contains the names of the clocks:
|
||||
"ic_clk", for the core clock used to generate the external I2C clock.
|
||||
"pclk", the interface clock, required for register access.
|
||||
|
||||
- reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
|
||||
time, named ICPU_CFG:TWI_DELAY in the datasheet.
|
||||
|
||||
- i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
|
||||
This option is only supported in hardware blocks version 1.11a or newer and
|
||||
on Microsemi SoCs ("mscc,ocelot-i2c" compatible).
|
||||
|
||||
- i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.
|
||||
This value which is by default 300ns is used to compute the tLOW period.
|
||||
|
||||
- i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
|
||||
This value which is by default 300ns is used to compute the tHIGH period.
|
||||
|
||||
Examples :
|
||||
|
||||
i2c@f0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xf0000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c@1120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x1120000 0x1000>;
|
||||
interrupt-parent = <&ictl>;
|
||||
interrupts = <12 1>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <300>;
|
||||
};
|
||||
|
||||
i2c@1120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2000 0x100>;
|
||||
clock-frequency = <400000>;
|
||||
clocks = <&i2cclk>;
|
||||
interrupts = <0>;
|
||||
|
||||
eeprom@64 {
|
||||
compatible = "linux,slave-24c02";
|
||||
reg = <0x40000064>;
|
||||
};
|
||||
};
|
||||
92
Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
Normal file
92
Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
Normal file
@ -0,0 +1,92 @@
|
||||
Qualcomm Camera Control Interface (CCI) I2C controller
|
||||
|
||||
PROPERTIES:
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be one of:
|
||||
"qcom,msm8916-cci"
|
||||
"qcom,msm8996-cci"
|
||||
"qcom,sdm845-cci"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: base address CCI I2C controller and length of memory
|
||||
mapped region.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: specifies the CCI I2C interrupt. The format of the
|
||||
specifier is defined by the binding document describing
|
||||
the node's interrupt parent.
|
||||
|
||||
- clocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: a list of phandle, should contain an entry for each
|
||||
entries in clock-names.
|
||||
|
||||
- clock-names
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: a list of clock names, must include "cci" clock.
|
||||
|
||||
- power-domains
|
||||
Usage: required for "qcom,msm8996-cci"
|
||||
Value type: <prop-encoded-array>
|
||||
Definition:
|
||||
|
||||
SUBNODES:
|
||||
|
||||
The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and
|
||||
sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1".
|
||||
|
||||
PROPERTIES:
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: Index of the CCI bus/master
|
||||
|
||||
- clock-frequency:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Desired I2C bus clock frequency in Hz, defaults to 100
|
||||
kHz if omitted.
|
||||
|
||||
Example:
|
||||
|
||||
cci@a0c000 {
|
||||
compatible = "qcom,msm8996-cci";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa0c000 0x1000>;
|
||||
interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
|
||||
<&mmcc CAMSS_TOP_AHB_CLK>,
|
||||
<&mmcc CAMSS_CCI_AHB_CLK>,
|
||||
<&mmcc CAMSS_CCI_CLK>,
|
||||
<&mmcc CAMSS_AHB_CLK>;
|
||||
clock-names = "mmss_mmagic_ahb",
|
||||
"camss_top_ahb",
|
||||
"cci_ahb",
|
||||
"cci",
|
||||
"camss_ahb";
|
||||
|
||||
i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
@ -2,32 +2,26 @@ Generic device tree bindings for I2C busses
|
||||
===========================================
|
||||
|
||||
This document describes generic bindings which can be used to describe I2C
|
||||
busses in a device tree.
|
||||
busses and their child devices in a device tree.
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
Required properties (per bus)
|
||||
-----------------------------
|
||||
|
||||
- #address-cells - should be <1>. Read more about addresses below.
|
||||
- #size-cells - should be <0>.
|
||||
- compatible - name of I2C bus controller following generic names
|
||||
recommended practice.
|
||||
- compatible - name of I2C bus controller
|
||||
|
||||
For other required properties e.g. to describe register sets,
|
||||
clocks, etc. check the binding documentation of the specific driver.
|
||||
|
||||
The cells properties above define that an address of children of an I2C bus
|
||||
are described by a single value. This is usually a 7 bit address. However,
|
||||
flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10
|
||||
bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address
|
||||
of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus.
|
||||
Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to
|
||||
be devices ourselves.
|
||||
are described by a single value.
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
Optional properties (per bus)
|
||||
-----------------------------
|
||||
|
||||
These properties may not be supported by all drivers. However, if a driver
|
||||
wants to support one of the below features, it should adapt the bindings below.
|
||||
wants to support one of the below features, it should adapt these bindings.
|
||||
|
||||
- clock-frequency
|
||||
frequency of bus clock in Hz.
|
||||
@ -73,6 +67,40 @@ wants to support one of the below features, it should adapt the bindings below.
|
||||
i2c bus clock frequency (clock-frequency).
|
||||
Specified in Hz.
|
||||
|
||||
- multi-master
|
||||
states that there is another master active on this bus. The OS can use
|
||||
this information to adapt power management to keep the arbitration awake
|
||||
all the time, for example. Can not be combined with 'single-master'.
|
||||
|
||||
- single-master
|
||||
states that there is no other master active on this bus. The OS can use
|
||||
this information to detect a stalled bus more reliably, for example.
|
||||
Can not be combined with 'multi-master'.
|
||||
|
||||
Required properties (per child device)
|
||||
--------------------------------------
|
||||
|
||||
- compatible
|
||||
name of I2C slave device
|
||||
|
||||
- reg
|
||||
One or many I2C slave addresses. These are usually a 7 bit addresses.
|
||||
However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is
|
||||
used to mark a 10 bit address. It is needed to avoid the ambiguity
|
||||
between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050
|
||||
which, in theory, can be on the same bus.
|
||||
Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we
|
||||
listen to be devices ourselves.
|
||||
|
||||
Optional properties (per child device)
|
||||
--------------------------------------
|
||||
|
||||
These properties may not be supported by all drivers. However, if a driver
|
||||
wants to support one of the below features, it should adapt these bindings.
|
||||
|
||||
- host-notify
|
||||
device uses SMBus host notify protocol instead of interrupt line.
|
||||
|
||||
- interrupts
|
||||
interrupts used by the device.
|
||||
|
||||
@ -80,24 +108,13 @@ wants to support one of the below features, it should adapt the bindings below.
|
||||
"irq", "wakeup" and "smbus_alert" names are recognized by I2C core,
|
||||
other names are left to individual drivers.
|
||||
|
||||
- host-notify
|
||||
device uses SMBus host notify protocol instead of interrupt line.
|
||||
|
||||
- multi-master
|
||||
states that there is another master active on this bus. The OS can use
|
||||
this information to adapt power management to keep the arbitration awake
|
||||
all the time, for example.
|
||||
|
||||
- wakeup-source
|
||||
device can be used as a wakeup source.
|
||||
|
||||
- reg
|
||||
I2C slave addresses
|
||||
|
||||
- reg-names
|
||||
Names of map programmable addresses.
|
||||
It can contain any map needing another address than default one.
|
||||
|
||||
- wakeup-source
|
||||
device can be used as a wakeup source.
|
||||
|
||||
Binding may contain optional "interrupts" property, describing interrupts
|
||||
used by the device. I2C core will assign "irq" interrupt (or the very first
|
||||
interrupt if not using interrupt names) as primary interrupt for the slave.
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: nuvoton NPCM7XX I2C Controller Device Tree Bindings
|
||||
|
||||
description: |
|
||||
The NPCM750x includes sixteen I2C bus controllers. All Controllers support
|
||||
both master and slave mode. Each controller can switch between master and slave
|
||||
at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and
|
||||
RX.
|
||||
|
||||
maintainers:
|
||||
- Tali Perry <tali.perry1@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nuvoton,npcm7xx-i2c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: Reference clock for the I2C bus
|
||||
|
||||
clock-frequency:
|
||||
description: Desired I2C bus clock frequency in Hz. If not specified,
|
||||
the default 100 kHz frequency will be used.
|
||||
possible values are 100000, 400000 and 1000000.
|
||||
default: 100000
|
||||
enum: [100000, 400000, 1000000]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
i2c0: i2c@80000 {
|
||||
reg = <0x80000 0x1000>;
|
||||
clocks = <&clk NPCM7XX_CLK_APB2>;
|
||||
clock-frequency = <100000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
compatible = "nuvoton,npcm750-i2c";
|
||||
};
|
||||
|
||||
...
|
||||
156
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
Normal file
156
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
Normal file
@ -0,0 +1,156 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synopsys DesignWare APB I2C Controller
|
||||
|
||||
maintainers:
|
||||
- Jarkko Nikula <jarkko.nikula@linux.intel.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
not:
|
||||
contains:
|
||||
const: mscc,ocelot-i2c
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Generic Synopsys DesignWare I2C controller
|
||||
const: snps,designware-i2c
|
||||
- description: Microsemi Ocelot SoCs I2C controller
|
||||
items:
|
||||
- const: mscc,ocelot-i2c
|
||||
- const: snps,designware-i2c
|
||||
- description: Baikal-T1 SoC System I2C controller
|
||||
const: baikal,bt1-sys-i2c
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: DW APB I2C controller memory mapped registers
|
||||
- description: |
|
||||
ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
|
||||
This registers are specific to the Ocelot I2C-controller.
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: I2C controller reference clock source
|
||||
- description: APB interface clock source
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: ref
|
||||
- const: pclk
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
description: Desired I2C bus clock frequency in Hz
|
||||
enum: [100000, 400000, 1000000, 3400000]
|
||||
default: 400000
|
||||
|
||||
i2c-sda-hold-time-ns:
|
||||
maxItems: 1
|
||||
description: |
|
||||
The property should contain the SDA hold time in nanoseconds. This option
|
||||
is only supported in hardware blocks version 1.11a or newer or on
|
||||
Microsemi SoCs.
|
||||
|
||||
i2c-scl-falling-time-ns:
|
||||
maxItems: 1
|
||||
description: |
|
||||
The property should contain the SCL falling time in nanoseconds.
|
||||
This value is used to compute the tLOW period.
|
||||
default: 300
|
||||
|
||||
i2c-sda-falling-time-ns:
|
||||
maxItems: 1
|
||||
description: |
|
||||
The property should contain the SDA falling time in nanoseconds.
|
||||
This value is used to compute the tHIGH period.
|
||||
default: 300
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: TX DMA Channel
|
||||
- description: RX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c@f0000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xf0000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <11>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
- |
|
||||
i2c@1120000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x1120000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <12 1>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <300>;
|
||||
};
|
||||
- |
|
||||
i2c@2000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x2000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <400000>;
|
||||
clocks = <&i2cclk>;
|
||||
interrupts = <0>;
|
||||
|
||||
eeprom@64 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x64>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
i2c@100400 {
|
||||
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
|
||||
reg = <0x100400 0x100>, <0x198 0x8>;
|
||||
pinctrl-0 = <&i2c_pins>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <8>;
|
||||
clocks = <&ahb_clk>;
|
||||
};
|
||||
...
|
||||
@ -81,11 +81,11 @@ properties:
|
||||
clock-frequency:
|
||||
description: Desired I2C bus clock frequency in Hz. If not specified,
|
||||
the default 100 kHz frequency will be used.
|
||||
For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode,
|
||||
Fast-mode and Fast-mode Plus are supported, possible
|
||||
values are 100000, 400000 and 1000000.
|
||||
For STM32F7, STM32H7 and STM32MP1 SoCs, if timing parameters
|
||||
match, the bus clock frequency can be from 1Hz to 1MHz.
|
||||
default: 100000
|
||||
enum: [100000, 400000, 1000000]
|
||||
minimum: 1
|
||||
maximum: 1000000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -67,8 +67,7 @@ properties:
|
||||
1 - direct_sync
|
||||
2 - scaled_sync
|
||||
3 - pulse_sync
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
|
||||
@ -25,9 +25,8 @@ properties:
|
||||
|
||||
amstaos,cover-comp-gain:
|
||||
description: Multiplier for gain compensation
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [1, 16]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 16]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -1,34 +0,0 @@
|
||||
Elantech I2C Touchscreen
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "elan,ekth3500".
|
||||
- reg: I2C address of the chip.
|
||||
- interrupts: interrupt to which the chip is connected (see interrupt
|
||||
binding[0]).
|
||||
|
||||
Optional properties:
|
||||
- wakeup-source: touchscreen can be used as a wakeup source.
|
||||
- pinctrl-names: should be "default" (see pinctrl binding [1]).
|
||||
- pinctrl-0: a phandle pointing to the pin settings for the device (see
|
||||
pinctrl binding [1]).
|
||||
- reset-gpios: reset gpio the chip is connected to.
|
||||
- vcc33-supply: a phandle for the regulator supplying 3.3V power.
|
||||
- vccio-supply: a phandle for the regulator supplying IO power.
|
||||
|
||||
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
Example:
|
||||
&i2c1 {
|
||||
/* ... */
|
||||
|
||||
touchscreen@10 {
|
||||
compatible = "elan,ekth3500";
|
||||
reg = <0x10>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
};
|
||||
555
Documentation/devicetree/bindings/input/iqs269a.yaml
Normal file
555
Documentation/devicetree/bindings/input/iqs269a.yaml
Normal file
@ -0,0 +1,555 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/iqs269a.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Azoteq IQS269A Capacitive Touch Controller
|
||||
|
||||
maintainers:
|
||||
- Jeff LaBundy <jeff@labundy.com>
|
||||
|
||||
description: |
|
||||
The Azoteq IQS269A is an 8-channel capacitive touch controller that features
|
||||
additional Hall-effect and inductive sensing capabilities.
|
||||
|
||||
Link to datasheet: https://www.azoteq.com/
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: azoteq,iqs269a
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
azoteq,hall-enable:
|
||||
type: boolean
|
||||
description:
|
||||
Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
|
||||
assigned to channel 6 are ignored and keycodes assigned to channel 7 are
|
||||
interpreted as switch codes. Refer to the datasheet for requirements im-
|
||||
posed on channels 6 and 7 by Hall-effect sensing.
|
||||
|
||||
azoteq,suspend-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description: |
|
||||
Specifies the power mode during suspend as follows:
|
||||
0: Automatic (same as normal runtime, i.e. suspend/resume disabled)
|
||||
1: Low power (all sensing at a reduced reporting rate)
|
||||
2: Ultra-low power (channel 0 proximity sensing)
|
||||
3: Halt (no sensing)
|
||||
|
||||
azoteq,clk-div:
|
||||
type: boolean
|
||||
description: Divides the device's core clock by a factor of 4.
|
||||
|
||||
azoteq,ulp-update:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
default: 3
|
||||
description: Specifies the ultra-low-power mode update rate.
|
||||
|
||||
azoteq,reseed-offset:
|
||||
type: boolean
|
||||
description:
|
||||
Applies an 8-count offset to all long-term averages upon either ATI or
|
||||
reseed events.
|
||||
|
||||
azoteq,filt-str-lp-lta:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description:
|
||||
Specifies the long-term average filter strength during low-power mode.
|
||||
|
||||
azoteq,filt-str-lp-cnt:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description:
|
||||
Specifies the raw count filter strength during low-power mode.
|
||||
|
||||
azoteq,filt-str-np-lta:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description:
|
||||
Specifies the long-term average filter strength during normal-power mode.
|
||||
|
||||
azoteq,filt-str-np-cnt:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description:
|
||||
Specifies the raw count filter strength during normal-power mode.
|
||||
|
||||
azoteq,rate-np-ms:
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
default: 16
|
||||
description: Specifies the report rate (in ms) during normal-power mode.
|
||||
|
||||
azoteq,rate-lp-ms:
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
default: 160
|
||||
description: Specifies the report rate (in ms) during low-power mode.
|
||||
|
||||
azoteq,rate-ulp-ms:
|
||||
multipleOf: 16
|
||||
minimum: 0
|
||||
maximum: 4080
|
||||
default: 160
|
||||
description: Specifies the report rate (in ms) during ultra-low-power mode.
|
||||
|
||||
azoteq,timeout-pwr-ms:
|
||||
multipleOf: 512
|
||||
minimum: 0
|
||||
maximum: 130560
|
||||
default: 2560
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait for an event during normal-
|
||||
power mode before transitioning to low-power mode.
|
||||
|
||||
azoteq,timeout-lta-ms:
|
||||
multipleOf: 512
|
||||
minimum: 0
|
||||
maximum: 130560
|
||||
default: 32768
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait before resetting the long-
|
||||
term average of all channels. Specify the maximum timeout to disable it
|
||||
altogether.
|
||||
|
||||
azoteq,ati-band-disable:
|
||||
type: boolean
|
||||
description: Disables the ATI band check.
|
||||
|
||||
azoteq,ati-lp-only:
|
||||
type: boolean
|
||||
description: Limits automatic ATI to low-power mode.
|
||||
|
||||
azoteq,ati-band-tighten:
|
||||
type: boolean
|
||||
description: Tightens the ATI band from 1/8 to 1/16 of the desired target.
|
||||
|
||||
azoteq,filt-disable:
|
||||
type: boolean
|
||||
description: Disables all raw count filtering.
|
||||
|
||||
azoteq,gpio3-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
default: 0
|
||||
description:
|
||||
Selects the channel for which the GPIO3 pin represents touch state.
|
||||
|
||||
azoteq,dual-direction:
|
||||
type: boolean
|
||||
description:
|
||||
Specifies that long-term averages are to freeze in the presence of either
|
||||
increasing or decreasing counts, thereby permitting events to be reported
|
||||
in either direction.
|
||||
|
||||
azoteq,tx-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description: |
|
||||
Specifies the inductive sensing excitation frequency as follows (paren-
|
||||
thesized numbers represent the frequency if 'azoteq,clk-div' is present):
|
||||
0: 16 MHz (4 MHz)
|
||||
1: 8 MHz (2 MHz)
|
||||
2: 4 MHz (1 MHz)
|
||||
3: 2 MHz (500 kHz)
|
||||
|
||||
azoteq,global-cap-increase:
|
||||
type: boolean
|
||||
description: Increases the global capacitance adder from 0.5 pF to 1.5 pF.
|
||||
|
||||
azoteq,reseed-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description: |
|
||||
Specifies the event(s) that prompt the device to reseed (i.e. reset the
|
||||
long-term average) of an associated channel as follows:
|
||||
0: None
|
||||
1: Proximity
|
||||
2: Proximity or touch
|
||||
3: Proximity, touch or deep touch
|
||||
|
||||
azoteq,tracking-enable:
|
||||
type: boolean
|
||||
description:
|
||||
Enables all associated channels to track their respective reference
|
||||
channels.
|
||||
|
||||
azoteq,filt-str-slider:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 1
|
||||
description: Specifies the slider coordinate filter strength.
|
||||
|
||||
patternProperties:
|
||||
"^channel@[0-7]$":
|
||||
type: object
|
||||
description:
|
||||
Represents a single sensing channel. A channel is active if defined and
|
||||
inactive otherwise.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description: Index of the channel.
|
||||
|
||||
azoteq,reseed-disable:
|
||||
type: boolean
|
||||
description:
|
||||
Prevents the channel from being reseeded if the long-term average
|
||||
timeout (defined in 'azoteq,timeout-lta') expires.
|
||||
|
||||
azoteq,blocking-enable:
|
||||
type: boolean
|
||||
description: Specifies that the channel is a blocking channel.
|
||||
|
||||
azoteq,slider0-select:
|
||||
type: boolean
|
||||
description: Specifies that the channel participates in slider 0.
|
||||
|
||||
azoteq,slider1-select:
|
||||
type: boolean
|
||||
description: Specifies that the channel participates in slider 1.
|
||||
|
||||
azoteq,rx-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Specifies the CRX pin(s) associated with the channel. By default, only
|
||||
the CRX pin corresponding to the channel's index is enabled (e.g. CRX0
|
||||
for channel 0).
|
||||
|
||||
azoteq,tx-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
default: [0, 1, 2, 3, 4, 5, 6, 7]
|
||||
description: Specifies the TX pin(s) associated with the channel.
|
||||
|
||||
azoteq,meas-cap-decrease:
|
||||
type: boolean
|
||||
description:
|
||||
Decreases the internal measurement capacitance from 60 pF to 15 pF.
|
||||
|
||||
azoteq,rx-float-inactive:
|
||||
type: boolean
|
||||
description: Floats any inactive CRX pins instead of grounding them.
|
||||
|
||||
azoteq,local-cap-size:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
default: 0
|
||||
description: |
|
||||
Specifies the capacitance to be added to the channel as follows:
|
||||
0: None
|
||||
1: Global adder (based on 'azoteq,global-cap-increase')
|
||||
2: Global adder + 0.5 pF
|
||||
|
||||
azoteq,invert-enable:
|
||||
type: boolean
|
||||
description:
|
||||
Inverts the polarity of the states reported for proximity, touch and
|
||||
deep-touch events relative to their respective thresholds.
|
||||
|
||||
azoteq,proj-bias:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 2
|
||||
description: |
|
||||
Specifies the bias current applied during projected-capacitance
|
||||
sensing as follows:
|
||||
0: 2.5 uA
|
||||
1: 5 uA
|
||||
2: 10 uA
|
||||
3: 20 uA
|
||||
|
||||
azoteq,sense-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 9, 14, 15]
|
||||
default: 0
|
||||
description: |
|
||||
Specifies the channel's sensing mode as follows:
|
||||
0: Self capacitance
|
||||
1: Projected capacitance
|
||||
9: Self or mutual inductance
|
||||
14: Hall effect
|
||||
15: Temperature
|
||||
|
||||
azoteq,sense-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 1
|
||||
description: |
|
||||
Specifies the channel's sensing frequency as follows (parenthesized
|
||||
numbers represent the frequency if 'azoteq,clk-div' is present):
|
||||
0: 4 MHz (1 MHz)
|
||||
1: 2 MHz (500 kHz)
|
||||
2: 1 MHz (250 kHz)
|
||||
3: 500 kHz (125 kHz)
|
||||
|
||||
azoteq,static-enable:
|
||||
type: boolean
|
||||
description: Enables the static front-end for the channel.
|
||||
|
||||
azoteq,ati-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 3
|
||||
description: |
|
||||
Specifies the channel's ATI mode as follows:
|
||||
0: Disabled
|
||||
1: Semi-partial
|
||||
2: Partial
|
||||
3: Full
|
||||
|
||||
azoteq,ati-base:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [75, 100, 150, 200]
|
||||
default: 100
|
||||
description: Specifies the channel's ATI base.
|
||||
|
||||
azoteq,ati-target:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
multipleOf: 32
|
||||
minimum: 0
|
||||
maximum: 2016
|
||||
default: 512
|
||||
description: Specifies the channel's ATI target.
|
||||
|
||||
azoteq,assoc-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Specifies the associated channels for which the channel serves as a
|
||||
reference channel. By default, no channels are selected.
|
||||
|
||||
azoteq,assoc-weight:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
default: 0
|
||||
description:
|
||||
Specifies the channel's impact weight if it acts as an associated
|
||||
channel (0 = 0% impact, 255 = 200% impact).
|
||||
|
||||
patternProperties:
|
||||
"^event-prox(-alt)?$":
|
||||
type: object
|
||||
description:
|
||||
Represents a proximity event reported by the channel in response to
|
||||
a decrease in counts. Node names suffixed with '-alt' instead corre-
|
||||
spond to an increase in counts.
|
||||
|
||||
By default, the long-term average tracks an increase in counts such
|
||||
that only events corresponding to a decrease in counts are reported
|
||||
(refer to the datasheet for more information).
|
||||
|
||||
Specify 'azoteq,dual-direction' to freeze the long-term average when
|
||||
the counts increase or decrease such that events of either direction
|
||||
can be reported. Alternatively, specify 'azoteq,invert-enable' to in-
|
||||
vert the polarity of the states reported by the channel.
|
||||
|
||||
Complementary events (e.g. event-touch and event-touch-alt) can both
|
||||
be present and specify different key or switch codes, but not differ-
|
||||
ent thresholds or hysteresis (if applicable).
|
||||
|
||||
properties:
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
default: 10
|
||||
description: Specifies the threshold for the event.
|
||||
|
||||
linux,code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Numeric key or switch code associated with the event.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
"^event-touch(-alt)?$":
|
||||
type: object
|
||||
description: Represents a touch event reported by the channel.
|
||||
|
||||
properties:
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
default: 8
|
||||
description: Specifies the threshold for the event.
|
||||
|
||||
azoteq,hyst:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
default: 4
|
||||
description: Specifies the hysteresis for the event.
|
||||
|
||||
linux,code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Numeric key or switch code associated with the event.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
"^event-deep(-alt)?$":
|
||||
type: object
|
||||
description: Represents a deep-touch event reported by the channel.
|
||||
|
||||
properties:
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
default: 26
|
||||
description: Specifies the threshold for the event.
|
||||
|
||||
azoteq,hyst:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
default: 0
|
||||
description: Specifies the hysteresis for the event.
|
||||
|
||||
linux,code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Numeric key or switch code associated with the event.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
iqs269a@44 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "azoteq,iqs269a";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
azoteq,hall-enable;
|
||||
azoteq,suspend-mode = <2>;
|
||||
|
||||
channel@0 {
|
||||
reg = <0x0>;
|
||||
|
||||
event-prox {
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
};
|
||||
|
||||
channel@1 {
|
||||
reg = <0x1>;
|
||||
azoteq,slider0-select;
|
||||
};
|
||||
|
||||
channel@2 {
|
||||
reg = <0x2>;
|
||||
azoteq,slider0-select;
|
||||
};
|
||||
|
||||
channel@3 {
|
||||
reg = <0x3>;
|
||||
azoteq,slider0-select;
|
||||
};
|
||||
|
||||
channel@4 {
|
||||
reg = <0x4>;
|
||||
azoteq,slider0-select;
|
||||
};
|
||||
|
||||
channel@5 {
|
||||
reg = <0x5>;
|
||||
azoteq,slider0-select;
|
||||
};
|
||||
|
||||
channel@6 {
|
||||
reg = <0x6>;
|
||||
azoteq,invert-enable;
|
||||
azoteq,static-enable;
|
||||
azoteq,reseed-disable;
|
||||
azoteq,rx-enable = <0>;
|
||||
azoteq,sense-freq = <0x0>;
|
||||
azoteq,sense-mode = <0xE>;
|
||||
azoteq,ati-mode = <0x0>;
|
||||
azoteq,ati-base = <200>;
|
||||
azoteq,ati-target = <320>;
|
||||
};
|
||||
|
||||
channel@7 {
|
||||
reg = <0x7>;
|
||||
azoteq,invert-enable;
|
||||
azoteq,static-enable;
|
||||
azoteq,reseed-disable;
|
||||
azoteq,rx-enable = <0>, <6>;
|
||||
azoteq,sense-freq = <0x0>;
|
||||
azoteq,sense-mode = <0xE>;
|
||||
azoteq,ati-mode = <0x3>;
|
||||
azoteq,ati-base = <200>;
|
||||
azoteq,ati-target = <320>;
|
||||
|
||||
event-touch {
|
||||
linux,code = <SW_LID>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,36 +0,0 @@
|
||||
* Device tree bindings for the Qualcomm MSM vibrator
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be one of
|
||||
"qcom,msm8226-vibrator"
|
||||
"qcom,msm8974-vibrator"
|
||||
- reg: the base address and length of the IO memory for the registers.
|
||||
- pinctrl-names: set to default.
|
||||
- pinctrl-0: phandles pointing to pin configuration nodes. See
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
- clock-names: set to pwm
|
||||
- clocks: phandle of the clock. See
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
- enable-gpios: GPIO that enables the vibrator.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- vcc-supply: phandle to the regulator that provides power to the sensor.
|
||||
|
||||
Example from a LG Nexus 5 (hammerhead) phone:
|
||||
|
||||
vibrator@fd8c3450 {
|
||||
reg = <0xfd8c3450 0x400>;
|
||||
compatible = "qcom,msm8974-vibrator";
|
||||
|
||||
vcc-supply = <&pm8941_l19>;
|
||||
|
||||
clocks = <&mmcc CAMSS_GP1_CLK>;
|
||||
clock-names = "pwm";
|
||||
|
||||
enable-gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vibrator_pin>;
|
||||
};
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/touchscreen/cypress,cy8ctma140.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cypress CY8CTMA140 series touchscreen controller bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: cypress,cy8ctma140
|
||||
|
||||
reg:
|
||||
const: 0x20
|
||||
|
||||
clock-frequency:
|
||||
description: I2C client clock frequency, defined for host
|
||||
minimum: 100000
|
||||
maximum: 400000
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
vcpin-supply:
|
||||
description: Analog power supply regulator on VCPIN pin
|
||||
|
||||
vdd-supply:
|
||||
description: Digital power supply regulator on VDD pin
|
||||
|
||||
touchscreen-inverted-x: true
|
||||
touchscreen-inverted-y: true
|
||||
touchscreen-size-x: true
|
||||
touchscreen-size-y: true
|
||||
touchscreen-swapped-x-y: true
|
||||
touchscreen-max-pressure: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- touchscreen-size-x
|
||||
- touchscreen-size-y
|
||||
- touchscreen-max-pressure
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
touchscreen@20 {
|
||||
compatible = "cypress,cy8ctma140";
|
||||
reg = <0x20>;
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <800>;
|
||||
touchscreen-max-pressure = <255>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
|
||||
vdd-supply = <&ab8500_ldo_aux2_reg>;
|
||||
vcpin-supply = <&ab8500_ldo_aux2_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/input/touchscreen/elan,elants_i2c.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Elantech I2C Touchscreen
|
||||
|
||||
maintainers:
|
||||
- David Heidelberg <david@ixit.cz>
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- elan,ektf3624
|
||||
- elan,ekth3500
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
wakeup-source:
|
||||
type: boolean
|
||||
description: touchscreen can be used as a wakeup source.
|
||||
|
||||
reset-gpios:
|
||||
description: reset gpio the chip is connected to.
|
||||
|
||||
vcc33-supply:
|
||||
description: a phandle for the regulator supplying 3.3V power.
|
||||
|
||||
vccio-supply:
|
||||
description: a phandle for the regulator supplying IO power.
|
||||
|
||||
touchscreen-inverted-x: true
|
||||
touchscreen-inverted-y: true
|
||||
touchscreen-size-x: true
|
||||
touchscreen-size-y: true
|
||||
touchscreen-swapped-x-y: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
touchscreen@10 {
|
||||
compatible = "elan,ekth3500";
|
||||
reg = <0x10>;
|
||||
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
@ -1,9 +1,10 @@
|
||||
* MELFAS MMS114/MMS152 touchscreen controller
|
||||
* MELFAS MMS114/MMS152/MMS345L touchscreen controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
- "melfas,mms114"
|
||||
- "melfas,mms152"
|
||||
- "melfas,mms345l"
|
||||
- reg: I2C address of the chip
|
||||
- interrupts: interrupt to which the chip is connected
|
||||
- touchscreen-size-x: See [1]
|
||||
|
||||
@ -25,19 +25,17 @@ properties:
|
||||
description:
|
||||
u32 value of the base of parent HyperTransport vector allocated
|
||||
to PCH MSI.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
- minimum: 0
|
||||
maximum: 255
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
|
||||
loongson,msi-num-vecs:
|
||||
description:
|
||||
u32 value of the number of parent HyperTransport vectors allocated
|
||||
to PCH MSI.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
- minimum: 1
|
||||
maximum: 256
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 1
|
||||
maximum: 256
|
||||
|
||||
msi-controller: true
|
||||
|
||||
|
||||
@ -25,10 +25,9 @@ properties:
|
||||
description:
|
||||
u32 value of the base of parent HyperTransport vector allocated
|
||||
to PCH PIC.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
- minimum: 0
|
||||
maximum: 192
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 192
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
|
||||
@ -31,9 +31,8 @@ properties:
|
||||
|
||||
reg-size:
|
||||
description: The access width of the register in bytes. Defaults to 1.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [1, 2, 4, 8]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 4, 8]
|
||||
|
||||
reg-spacing:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
@ -43,9 +42,8 @@ properties:
|
||||
description: |
|
||||
The amount of bits to shift the register content to the right to get
|
||||
the data into bit zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- maximum: 56
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 56
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -57,8 +57,7 @@ properties:
|
||||
description: |
|
||||
mA; per-string current limit.
|
||||
This property is supported only for WLED3.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 20
|
||||
minimum: 0
|
||||
maximum: 25
|
||||
@ -74,38 +73,33 @@ properties:
|
||||
qcom,current-boost-limit:
|
||||
description: |
|
||||
mA; boost current limit.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,switching-freq:
|
||||
description: |
|
||||
kHz; switching frequency.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, 1600, 1920, 2400, 3200, 4800, 9600 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, 1600, 1920, 2400, 3200, 4800, 9600 ]
|
||||
|
||||
qcom,ovp:
|
||||
description: |
|
||||
V; Over-voltage protection limit.
|
||||
This property is supported only for WLED3.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 27, 29, 32, 35 ]
|
||||
- default: 29
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 27, 29, 32, 35 ]
|
||||
default: 29
|
||||
|
||||
qcom,ovp-millivolt:
|
||||
description: |
|
||||
Over-voltage protection limit. This property is for WLED4 only.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 18100, 19600, 29600, 31100 ]
|
||||
- default: 29600
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 18100, 19600, 29600, 31100 ]
|
||||
default: 29600
|
||||
|
||||
qcom,num-strings:
|
||||
description: |
|
||||
number of led strings attached.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,enabled-strings:
|
||||
description: |
|
||||
@ -113,8 +107,7 @@ properties:
|
||||
string of leds are operated individually. Specify the
|
||||
list of strings used by the device. Any combination of
|
||||
led strings can be used.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
@ -150,10 +143,9 @@ properties:
|
||||
0 - Modulator A
|
||||
1 - Modulator B
|
||||
This property is applicable only to WLED5 peripheral.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
- default: 0
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1 ]
|
||||
default: 0
|
||||
|
||||
qcom,cabc-sel:
|
||||
description: |
|
||||
@ -164,9 +156,8 @@ properties:
|
||||
2 - CABC 2
|
||||
3 - External signal (e.g. LPG) is used for dimming
|
||||
This property is applicable only to WLED5 peripheral.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1, 2, 3 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
|
||||
@ -32,8 +32,7 @@ properties:
|
||||
patternProperties:
|
||||
"^led@[0-2]$":
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: common.yaml#
|
||||
$ref: common.yaml#
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
||||
@ -33,8 +33,7 @@ properties:
|
||||
|
||||
led:
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: common.yaml#
|
||||
$ref: common.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -1,88 +0,0 @@
|
||||
Binding for the Qualcomm APCS global block
|
||||
==========================================
|
||||
|
||||
This binding describes the APCS "global" block found in various Qualcomm
|
||||
platforms.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be one of:
|
||||
"qcom,msm8916-apcs-kpss-global",
|
||||
"qcom,msm8996-apcs-hmss-global"
|
||||
"qcom,msm8998-apcs-hmss-global"
|
||||
"qcom,qcs404-apcs-apps-global"
|
||||
"qcom,sc7180-apss-shared"
|
||||
"qcom,sdm845-apss-shared"
|
||||
"qcom,sm8150-apss-shared"
|
||||
"qcom,ipq8074-apcs-apps-global"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: must specify the base address and size of the global block
|
||||
|
||||
- clocks:
|
||||
Usage: required if #clock-names property is present
|
||||
Value type: <phandle array>
|
||||
Definition: phandles to the two parent clocks of the clock driver.
|
||||
|
||||
- #mbox-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: as described in mailbox.txt, must be 1
|
||||
|
||||
- #clock-cells:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: as described in clock.txt, must be 0
|
||||
|
||||
- clock-names:
|
||||
Usage: required if the platform data based clock driver needs to
|
||||
retrieve the parent clock names from device tree.
|
||||
This will requires two mandatory clocks to be defined.
|
||||
Value type: <string-array>
|
||||
Definition: must be "pll" and "aux"
|
||||
|
||||
= EXAMPLE
|
||||
The following example describes the APCS HMSS found in MSM8996 and part of the
|
||||
GLINK RPM referencing the "rpm_hlos" doorbell therein.
|
||||
|
||||
apcs_glb: mailbox@9820000 {
|
||||
compatible = "qcom,msm8996-apcs-hmss-global";
|
||||
reg = <0x9820000 0x1000>;
|
||||
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
rpm-glink {
|
||||
compatible = "qcom,glink-rpm";
|
||||
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
||||
|
||||
mboxes = <&apcs_glb 0>;
|
||||
mbox-names = "rpm_hlos";
|
||||
};
|
||||
|
||||
Below is another example of the APCS binding on MSM8916 platforms:
|
||||
|
||||
apcs: mailbox@b011000 {
|
||||
compatible = "qcom,msm8916-apcs-kpss-global";
|
||||
reg = <0xb011000 0x1000>;
|
||||
#mbox-cells = <1>;
|
||||
clocks = <&a53pll>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
Below is another example of the APCS binding on QCS404 platforms:
|
||||
|
||||
apcs_glb: mailbox@b011000 {
|
||||
compatible = "qcom,qcs404-apcs-apps-global", "syscon";
|
||||
reg = <0x0b011000 0x1000>;
|
||||
#mbox-cells = <1>;
|
||||
clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
|
||||
clock-names = "pll", "aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Qualcomm APCS global block bindings
|
||||
|
||||
description:
|
||||
This binding describes the APCS "global" block found in various Qualcomm
|
||||
platforms.
|
||||
|
||||
maintainers:
|
||||
- Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq8074-apcs-apps-global
|
||||
- qcom,msm8916-apcs-kpss-global
|
||||
- qcom,msm8996-apcs-hmss-global
|
||||
- qcom,msm8998-apcs-hmss-global
|
||||
- qcom,qcs404-apcs-apps-global
|
||||
- qcom,sc7180-apss-shared
|
||||
- qcom,sdm845-apss-shared
|
||||
- qcom,sm8150-apss-shared
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: phandles to the parent clocks of the clock driver
|
||||
items:
|
||||
- description: primary pll parent of the clock driver
|
||||
- description: auxiliary parent
|
||||
|
||||
'#mbox-cells':
|
||||
const: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pll
|
||||
- const: aux
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#mbox-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
# Example apcs with msm8996
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
apcs_glb: mailbox@9820000 {
|
||||
compatible = "qcom,msm8996-apcs-hmss-global";
|
||||
reg = <0x9820000 0x1000>;
|
||||
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
rpm-glink {
|
||||
compatible = "qcom,glink-rpm";
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
||||
mboxes = <&apcs_glb 0>;
|
||||
mbox-names = "rpm_hlos";
|
||||
};
|
||||
|
||||
# Example apcs with qcs404
|
||||
- |
|
||||
#define GCC_APSS_AHB_CLK_SRC 1
|
||||
#define GCC_GPLL0_AO_OUT_MAIN 123
|
||||
apcs: mailbox@b011000 {
|
||||
compatible = "qcom,qcs404-apcs-apps-global";
|
||||
reg = <0x0b011000 0x1000>;
|
||||
#mbox-cells = <1>;
|
||||
clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
|
||||
clock-names = "pll", "aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
80
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
Normal file
80
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
Normal file
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
The Inter-Processor Communication Controller (IPCC) is a centralized hardware
|
||||
to route interrupts across various subsystems. It involves a three-level
|
||||
addressing scheme called protocol, client and signal. For example, consider an
|
||||
entity on the Application Processor Subsystem (APSS) that wants to listen to
|
||||
Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
|
||||
a case, the client would be Modem (client-id is 2) and the signal would be
|
||||
SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
|
||||
protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
|
||||
for the list of such IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,sm8250-ipcc
|
||||
- const: qcom,ipcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 3
|
||||
description:
|
||||
The first cell is the client-id, the second cell is the signal-id and the
|
||||
third cell is the interrupt type.
|
||||
|
||||
"#mbox-cells":
|
||||
const: 2
|
||||
description:
|
||||
The first cell is the client-id, and the second cell is the signal-id.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
- "#mbox-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/qcom-ipcc.h>
|
||||
|
||||
mailbox@408000 {
|
||||
compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
|
||||
reg = <0x408000 0x1000>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
smp2p-modem {
|
||||
compatible = "qcom,smp2p";
|
||||
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS
|
||||
IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
|
||||
/* Other SMP2P fields */
|
||||
};
|
||||
60
Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml
Normal file
60
Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Spreadtrum mailbox controller bindings
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
- Baolin Wang <baolin.wang7@gmail.com>
|
||||
- Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- sprd,sc9860-mailbox
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: inbox registers' base address
|
||||
- description: outbox registers' base address
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: inbox interrupt
|
||||
- description: outbox interrupt
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: enable
|
||||
|
||||
"#mbox-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#mbox-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
mailbox: mailbox@400a0000 {
|
||||
compatible = "sprd,sc9860-mailbox";
|
||||
reg = <0x400a0000 0x8000>, <0x400a8000 0x8000>;
|
||||
#mbox-cells = <1>;
|
||||
clock-names = "enable";
|
||||
clocks = <&aon_gate 53>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
...
|
||||
@ -79,8 +79,7 @@ properties:
|
||||
- const: 4
|
||||
|
||||
link-frequencies:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint64-array
|
||||
$ref: /schemas/types.yaml#/definitions/uint64-array
|
||||
description:
|
||||
Allowed data bus frequencies. 360000000, 180000000 Hz or both
|
||||
are supported by the driver.
|
||||
|
||||
@ -61,7 +61,7 @@ examples:
|
||||
|
||||
vdec: video-codec@ff660000 {
|
||||
compatible = "rockchip,rk3399-vdec";
|
||||
reg = <0x0 0xff660000 0x0 0x400>;
|
||||
reg = <0xff660000 0x400>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
|
||||
<&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
|
||||
|
||||
@ -66,7 +66,7 @@ examples:
|
||||
|
||||
vpu: video-codec@ff9a0000 {
|
||||
compatible = "rockchip,rk3288-vpu";
|
||||
reg = <0x0 0xff9a0000 0x0 0x800>;
|
||||
reg = <0xff9a0000 0x800>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "vepu", "vdpu";
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user