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Merge tag 'mvebu-clk-4.1' of git://git.infradead.org/linux-mvebu into clk-next
clock changes for mvebu for v4.1 - Add clock support for Armada 39x
This commit is contained in:
commit
0833b5ae69
@ -23,6 +23,14 @@ The following is a list of provided IDs and clock names on Armada 380/385:
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2 = l2clk (L2 Cache clock)
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3 = ddrclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 39x:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = nbclk (Coherent Fabric clock)
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3 = hclk (SDRAM Controller Internal Clock)
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4 = dclk (SDRAM Interface Clock)
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5 = refclk (Reference Clock)
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The following is a list of provided IDs and clock names on Kirkwood and Dove:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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@ -39,6 +47,7 @@ Required properties:
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"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
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"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
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"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
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"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
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"marvell,dove-core-clock" - for Dove SoC core clocks
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"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
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@ -1,6 +1,6 @@
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* Gated Clock bindings for Marvell EBU SoCs
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Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
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Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
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peripheral clocks to be gated to save some power. The clock consumer
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should specify the desired clock by having the clock ID in its
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"clocks" phandle cell. The clock ID is directly mapped to the
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@ -77,6 +77,18 @@ ID Clock Peripheral
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28 xor1 XOR 1
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30 sata1 SATA 1
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The following is a list of provided IDs for Armada 39x:
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ID Clock Peripheral
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-----------------------------------
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5 pex1 PCIe 1
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6 pex2 PCIe 2
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7 pex3 PCIe 3
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8 pex0 PCIe 0
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9 usb3h0 USB3 Host 0
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17 sdio SDIO
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22 xor0 XOR 0
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28 xor1 XOR 1
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The following is a list of provided IDs for Armada XP:
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ID Clock Peripheral
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-----------------------------------
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@ -152,6 +164,7 @@ Required properties:
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"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
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"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
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"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
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"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
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"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
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"marvell,dove-gating-clock" - for Dove SoC clock gating
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"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
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@ -21,6 +21,10 @@ config ARMADA_38X_CLK
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bool
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select MVEBU_CLK_COMMON
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config ARMADA_39X_CLK
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bool
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select MVEBU_CLK_COMMON
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config ARMADA_XP_CLK
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bool
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select MVEBU_CLK_COMMON
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@ -5,6 +5,7 @@ obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
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obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
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obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o
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obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o
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obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o
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obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
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obj-$(CONFIG_DOVE_CLK) += dove.o
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obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
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156
drivers/clk/mvebu/armada-39x.c
Normal file
156
drivers/clk/mvebu/armada-39x.c
Normal file
@ -0,0 +1,156 @@
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/*
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* Marvell Armada 39x SoC clocks
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*
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* Copyright (C) 2015 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "common.h"
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/*
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* SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
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*
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* SARL[15] : TCLK frequency
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* 0 = 250 MHz
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* 1 = 200 MHz
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*
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* SARH[0] : Reference clock frequency
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* 0 = 25 Mhz
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* 1 = 40 Mhz
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*/
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#define SARL 0
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#define SARL_A390_TCLK_FREQ_OPT 15
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#define SARL_A390_TCLK_FREQ_OPT_MASK 0x1
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#define SARL_A390_CPU_DDR_L2_FREQ_OPT 10
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#define SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
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#define SARH 4
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#define SARH_A390_REFCLK_FREQ BIT(0)
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static const u32 armada_39x_tclk_frequencies[] __initconst = {
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250000000,
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200000000,
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};
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static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
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{
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u8 tclk_freq_select;
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tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
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SARL_A390_TCLK_FREQ_OPT_MASK);
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return armada_39x_tclk_frequencies[tclk_freq_select];
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}
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static const u32 armada_39x_cpu_frequencies[] __initconst = {
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[0x0] = 666 * 1000 * 1000,
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[0x2] = 800 * 1000 * 1000,
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[0x3] = 800 * 1000 * 1000,
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[0x4] = 1066 * 1000 * 1000,
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[0x5] = 1066 * 1000 * 1000,
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[0x6] = 1200 * 1000 * 1000,
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[0x8] = 1332 * 1000 * 1000,
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[0xB] = 1600 * 1000 * 1000,
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[0xC] = 1600 * 1000 * 1000,
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[0x12] = 1800 * 1000 * 1000,
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[0x1E] = 1800 * 1000 * 1000,
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};
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static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
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{
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u8 cpu_freq_select;
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cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
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SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
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if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
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pr_err("Selected CPU frequency (%d) unsupported\n",
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cpu_freq_select);
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return 0;
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}
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return armada_39x_cpu_frequencies[cpu_freq_select];
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}
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enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
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static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
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{ .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
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{ .id = A390_CPU_TO_HCLK, .name = "hclk" },
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{ .id = A390_CPU_TO_DCLK, .name = "dclk" },
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};
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static void __init armada_39x_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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switch (id) {
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case A390_CPU_TO_NBCLK:
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*mult = 1;
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*div = 2;
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break;
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case A390_CPU_TO_HCLK:
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*mult = 1;
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*div = 4;
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break;
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case A390_CPU_TO_DCLK:
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*mult = 1;
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*div = 2;
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break;
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}
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}
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static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
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{
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if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
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return 40 * 1000 * 1000;
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else
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return 25 * 1000 * 1000;
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}
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static const struct coreclk_soc_desc armada_39x_coreclks = {
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.get_tclk_freq = armada_39x_get_tclk_freq,
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.get_cpu_freq = armada_39x_get_cpu_freq,
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.get_clk_ratio = armada_39x_get_clk_ratio,
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.get_refclk_freq = armada_39x_refclk_ratio,
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.ratios = armada_39x_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
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};
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static void __init armada_39x_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &armada_39x_coreclks);
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}
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CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
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armada_39x_coreclk_init);
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/*
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* Clock Gating Control
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*/
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static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
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{ "pex1", NULL, 5 },
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{ "pex2", NULL, 6 },
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{ "pex3", NULL, 7 },
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{ "pex0", NULL, 8 },
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{ "usb3h0", NULL, 9 },
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{ "sdio", NULL, 17 },
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{ "xor0", NULL, 22 },
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{ "xor1", NULL, 28 },
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{ }
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};
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static void __init armada_39x_clk_gating_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, armada_39x_gating_desc);
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}
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CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
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armada_39x_clk_gating_init);
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@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
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/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
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clk_data.clk_num = 2 + desc->num_ratios;
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/* One more clock for the optional refclk */
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if (desc->get_refclk_freq)
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clk_data.clk_num += 1;
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clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
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GFP_KERNEL);
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if (WARN_ON(!clk_data.clks)) {
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@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
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WARN_ON(IS_ERR(clk_data.clks[2+n]));
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};
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/* Register optional refclk */
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if (desc->get_refclk_freq) {
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const char *name = "refclk";
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of_property_read_string_index(np, "clock-output-names",
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2 + desc->num_ratios, &name);
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rate = desc->get_refclk_freq(base);
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clk_data.clks[2 + desc->num_ratios] =
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clk_register_fixed_rate(NULL, name, NULL,
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CLK_IS_ROOT, rate);
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WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
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}
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/* SAR register isn't needed anymore */
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iounmap(base);
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@ -30,6 +30,7 @@ struct coreclk_soc_desc {
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u32 (*get_tclk_freq)(void __iomem *sar);
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u32 (*get_cpu_freq)(void __iomem *sar);
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void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
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u32 (*get_refclk_freq)(void __iomem *sar);
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bool (*is_sscg_enabled)(void __iomem *sar);
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u32 (*fix_sscg_deviation)(u32 system_clk);
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const struct coreclk_ratio *ratios;
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