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ARM: pm: omap34xx: convert to generic suspend/resume support
Convert omap34xx to use the generic CPU suspend/resume support, rather than implementing its own version. Tested on 3430 LDP. Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King
parent
2637ce30e1
commit
076f2cc449
@ -40,8 +40,6 @@
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#include <plat/gpmc.h>
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#include <plat/dma.h>
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#include <asm/tlbflush.h>
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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@ -64,11 +62,6 @@ static inline bool is_suspending(void)
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}
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#endif
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/* Scratchpad offsets */
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#define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
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#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
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#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
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/* pm34xx errata defined in pm.h */
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u16 pm34xx_errata;
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@ -312,28 +305,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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/* Function to restore the table entry that was modified for enabling MMU */
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static void restore_table_entry(void)
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static void omap34xx_do_sram_idle(unsigned long save_state)
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{
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void __iomem *scratchpad_address;
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u32 previous_value, control_reg_value;
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u32 *address;
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scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
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/* Get address of entry that was modified */
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address = (u32 *)__raw_readl(scratchpad_address +
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OMAP343X_TABLE_ADDRESS_OFFSET);
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/* Get the previous value which needs to be restored */
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previous_value = __raw_readl(scratchpad_address +
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OMAP343X_TABLE_VALUE_OFFSET);
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address = __va(address);
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*address = previous_value;
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flush_tlb_all();
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control_reg_value = __raw_readl(scratchpad_address
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+ OMAP343X_CONTROL_REG_VALUE_OFFSET);
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/* This will enable caches and prediction */
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set_cr(control_reg_value);
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_omap_sram_idle(omap3_arm_context, save_state);
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}
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void omap_sram_idle(void)
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@ -432,12 +406,15 @@ void omap_sram_idle(void)
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sdrc_pwr = sdrc_read_reg(SDRC_POWER);
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/*
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* omap3_arm_context is the location where ARM registers
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* get saved. The restore path then reads from this
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* location and restores them back.
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* omap3_arm_context is the location where some ARM context
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* get saved. The rest is placed on the stack, and restored
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* from there before resuming.
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*/
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_omap_sram_idle(omap3_arm_context, save_state);
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cpu_init();
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if (save_state == 1 || save_state == 3)
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cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, save_state,
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omap34xx_do_sram_idle);
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else
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omap34xx_do_sram_idle(save_state);
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/* Restore normal SDRC POWER settings */
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if (omap_rev() >= OMAP3430_REV_ES3_0 &&
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@ -445,10 +422,6 @@ void omap_sram_idle(void)
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core_next_state == PWRDM_POWER_OFF)
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sdrc_write_reg(sdrc_pwr, SDRC_POWER);
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/* Restore table entry modified during MMU restoration */
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if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
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restore_table_entry();
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/* CORE */
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if (core_next_state < PWRDM_POWER_ON) {
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core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
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@ -211,37 +211,6 @@ save_context_wfi:
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mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
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stmia r8!, {r4-r5} @ Push parameters for restore call
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/* Check what that target sleep state is from r1 */
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cmp r1, #0x2 @ Only L2 lost, no need to save context
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beq clean_caches
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l1_logic_lost:
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mov r4, sp @ Store sp
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mrs r5, spsr @ Store spsr
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mov r6, lr @ Store lr
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stmia r8!, {r4-r6}
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mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
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mrc p15, 0, r5, c2, c0, 0 @ TTBR0
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mrc p15, 0, r6, c2, c0, 1 @ TTBR1
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mrc p15, 0, r7, c2, c0, 2 @ TTBCR
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mrc p15, 0, r5, c10, c2, 0 @ PRRR
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mrc p15, 0, r6, c10, c2, 1 @ NMRR
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stmia r8!,{r4-r6}
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mrc p15, 0, r4, c13, c0, 1 @ Context ID
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mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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mrs r7, cpsr @ Store current cpsr
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c1, c0, 0 @ save control register
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stmia r8!, {r4}
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clean_caches:
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/*
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* jump out to kernel flush routine
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* - reuse that code is better
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@ -466,109 +435,11 @@ logic_l1_restore:
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orr r1, r1, #2 @ re-enable L2 cache
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mcr p15, 0, r1, c1, c0, 1
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skipl2reen:
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mov r1, #0
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/*
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* Invalidate all instruction caches to PoU
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* and flush branch target cache
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*/
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mcr p15, 0, r1, c7, c5, 0
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ldr r4, scratchpad_base
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ldr r3, [r4,#0xBC]
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adds r3, r3, #16
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ldmia r3!, {r4-r6}
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mov sp, r4 @ Restore sp
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msr spsr_cxsf, r5 @ Restore spsr
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mov lr, r6 @ Restore lr
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ldmia r3!, {r4-r7}
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mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
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mcr p15, 0, r5, c2, c0, 0 @ TTBR0
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mcr p15, 0, r6, c2, c0, 1 @ TTBR1
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mcr p15, 0, r7, c2, c0, 2 @ TTBCR
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ldmia r3!,{r4-r6}
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mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mcr p15, 0, r5, c10, c2, 0 @ PRRR
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mcr p15, 0, r6, c10, c2, 1 @ NMRR
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ldmia r3!,{r4-r7}
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mcr p15, 0, r4, c13, c0, 1 @ Context ID
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mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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msr cpsr, r7 @ store cpsr
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/* Enabling MMU here */
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mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
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/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
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and r7, #0x7
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cmp r7, #0x0
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beq usettbr0
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ttbr_error:
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/*
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* More work needs to be done to support N[0:2] value other than 0
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* So looping here so that the error can be detected
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*/
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b ttbr_error
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usettbr0:
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mrc p15, 0, r2, c2, c0, 0
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ldr r5, ttbrbit_mask
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and r2, r5
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mov r4, pc
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ldr r5, table_index_mask
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and r4, r5 @ r4 = 31 to 20 bits of pc
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/* Extract the value to be written to table entry */
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ldr r1, table_entry
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/* r1 has the value to be written to table entry*/
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add r1, r1, r4
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/* Getting the address of table entry to modify */
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lsr r4, #18
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/* r2 has the location which needs to be modified */
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add r2, r4
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/* Storing previous entry of location being modified */
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ldr r5, scratchpad_base
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ldr r4, [r2]
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str r4, [r5, #0xC0]
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/* Modify the table entry */
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str r1, [r2]
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/*
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* Storing address of entry being modified
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* - will be restored after enabling MMU
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*/
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ldr r5, scratchpad_base
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str r2, [r5, #0xC4]
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
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mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
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mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
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mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
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/*
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* Restore control register. This enables the MMU.
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* The caches and prediction are not enabled here, they
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* will be enabled after restoring the MMU table entry.
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*/
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ldmia r3!, {r4}
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/* Store previous value of control register in scratchpad */
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str r4, [r5, #0xC8]
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ldr r2, cache_pred_disable_mask
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and r4, r2
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mcr p15, 0, r4, c1, c0, 0
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dsb
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isb
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ldr r0, =restoremmu_on
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bx r0
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/*
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* ==============================
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* == Exit point from OFF mode ==
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* ==============================
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*/
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restoremmu_on:
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ldmfd sp!, {r4 - r11, pc} @ restore regs and return
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/* Now branch to the common CPU resume function */
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b cpu_resume
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.ltorg
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/*
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* Internal functions
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@ -719,14 +590,6 @@ sram_base:
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.word SRAM_BASE_P + 0x8000
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sdrc_power:
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.word SDRC_POWER_V
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ttbrbit_mask:
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.word 0xFFFFC000
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table_index_mask:
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.word 0xFFF00000
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table_entry:
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.word 0x00000C02
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cache_pred_disable_mask:
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.word 0xFFFFE7FB
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control_stat:
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.word CONTROL_STAT
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control_mem_rta:
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