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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 06:56:46 +07:00
hsu: some code cleanup
Major changes are: * refine the comments in the driver * remove unused member from structure "hsu_port" * extended spin_lock protoction for dma mode in port_irq() Signed-off-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Feng Tang
Greg Kroah-Hartman
parent
669b7a0938
commit
06c77e21ae
@ -3,7 +3,7 @@
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*
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* Refer pxa.c, 8250.c and some other drivers in drivers/serial/
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*
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* (C) Copyright 2009 Intel Corporation
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* (C) Copyright 2010 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -11,30 +11,16 @@
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* of the License.
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*/
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/* Notes:
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* 1. there should be 2 types of register access method, one for
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* UART ports, the other for the general purpose registers
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* 1. DMA channel allocation: 0/1 channel are assigned to port 0,
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* 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
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* are used for RX, odd chans for TX
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*
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* 2. It used to have a Irda port, but was defeatured recently
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* 2. In A0 stepping, UART will not support TX half empty flag
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*
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* 3. Based on the info from HSU MAS, 0/1 channel are assigned to
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* port0, 2/3 chan to port 1, 4/5 chan to port 3. Even number
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* chan will be read, odd chan for write
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*
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* 4. HUS supports both the 64B and 16B FIFO version, but this driver
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* will only use 64B version
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*
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* 5. In A0 stepping, UART will not support TX half empty flag, thus
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* need add a #ifdef judgement
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*
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* 6. One more bug for A0, the loopback mode won't support AFC
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* auto-flow control
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*
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* 7. HSU has some special FCR control bits, we add it to serial_reg.h
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*
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* 8. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always asserted,
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* only when the HW is reset the DDCD and DDSR will be triggered
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* 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
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* asserted, only when the HW is reset the DDCD and DDSR will
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* be triggered
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*/
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#include <linux/module.h>
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@ -75,7 +61,7 @@ struct hsu_dma_buffer {
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struct hsu_dma_chan {
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u32 id;
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u32 dirt; /* to or from device */
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enum dma_data_direction dirt;
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struct uart_hsu_port *uport;
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void __iomem *reg;
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struct timer_list rx_timer; /* only needed by RX channel */
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@ -102,8 +88,6 @@ struct uart_hsu_port {
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/* Top level data structure of HSU */
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struct hsu_port {
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struct pci_device *pdev;
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void __iomem *reg;
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unsigned long paddr;
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unsigned long iolen;
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@ -112,23 +96,9 @@ struct hsu_port {
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struct uart_hsu_port port[3];
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struct hsu_dma_chan chans[10];
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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};
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static inline void hexdump(char *str, u8 *addr, int cnt)
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{
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int i;
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for (i = 0; i < cnt; i += 8) {
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printk("0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
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addr[i], addr[i+1], addr[i+2], addr[i+3],
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addr[i+4], addr[i+5], addr[i+6], addr[i+7]);
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printk("\n");
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}
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}
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static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
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{
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unsigned int val;
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@ -353,9 +323,6 @@ void hsu_dma_tx(struct uart_hsu_port *up)
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| (0x1 << 8)
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| (0x1 << 16)
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| (0x1 << 24));
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WARN(chan_readl(up->txc, HSU_CH_CR) & 0x1,
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"TX channel has already be started!!\n");
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up->dma_tx_on = 1;
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chan_writel(up->txc, HSU_CH_CR, 0x1);
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}
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@ -367,7 +334,6 @@ void hsu_dma_tx(struct uart_hsu_port *up)
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/* The buffer is already cache coherent */
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void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
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{
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/* Need start RX dma channel here */
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dbuf->ofs = 0;
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chan_writel(rxc, HSU_CH_BSR, 32);
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@ -426,35 +392,32 @@ void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
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return;
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/*
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* first need to know how many is already transferred,
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* First need to know how many is already transferred,
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* then check if its a timeout DMA irq, and return
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* the trail bytes out, push them up and reenable the
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* channel, better to use 2 descriptors at the same time
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* channel
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*/
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/* timeout IRQ, need wait some time, see Errata 2 */
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/* Timeout IRQ, need wait some time, see Errata 2 */
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if (int_sts & 0xf00)
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udelay(2);
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/* Stop the channel */
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chan_writel(chan, HSU_CH_CR, 0x0);
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/* We can use 2 ways to calc the actual transfer len */
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count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
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if (!count) {
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/* restart the channel before we leave */
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/* Restart the channel before we leave */
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chan_writel(chan, HSU_CH_CR, 0x3);
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return;
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}
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del_timer(&chan->rx_timer);
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dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
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dbuf->dma_size, DMA_FROM_DEVICE);
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/*
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* head will only wrap around when we recycle
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* Head will only wrap around when we recycle
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* the DMA buffer, and when that happens, we
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* explicitly set tail to 0. So head will
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* always be greater than tail.
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@ -496,10 +459,6 @@ static void serial_hsu_stop_rx(struct uart_port *port)
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}
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}
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/*
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* if there is error flag, should we just reset the FIFO or keeps
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* working on it
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*/
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static inline void receive_chars(struct uart_hsu_port *up, int *status)
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{
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struct tty_struct *tty = up->port.state->port.tty;
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@ -571,7 +530,6 @@ static void transmit_chars(struct uart_hsu_port *up)
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{
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struct circ_buf *xmit = &up->port.state->xmit;
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int count;
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int i = 0; /* for debug use */
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if (up->port.x_char) {
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serial_out(up, UART_TX, up->port.x_char);
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@ -592,13 +550,11 @@ static void transmit_chars(struct uart_hsu_port *up)
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* into it won't clear the EMPT bit, so we may need be cautious
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* by useing a shorter buffer
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*/
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/* count = up->port.fifosize; */
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count = up->port.fifosize - 4;
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#endif
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do {
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serial_out(up, UART_TX, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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i++;
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up->port.icount.tx++;
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if (uart_circ_empty(xmit))
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@ -628,7 +584,7 @@ static inline void check_modem_status(struct uart_hsu_port *up)
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/* We may only get DDCD when HW init and reset */
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if (status & UART_MSR_DDCD)
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uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
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/* will start/stop_tx accordingly */
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/* Will start/stop_tx accordingly */
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if (status & UART_MSR_DCTS)
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uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
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@ -647,6 +603,7 @@ static irqreturn_t port_irq(int irq, void *dev_id)
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if (unlikely(!up->running))
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return IRQ_NONE;
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spin_lock_irqsave(&up->port.lock, flags);
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if (up->use_dma) {
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lsr = serial_in(up, UART_LSR);
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if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
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@ -655,10 +612,10 @@ static irqreturn_t port_irq(int irq, void *dev_id)
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"Got lsr irq while using DMA, lsr = 0x%2x\n",
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lsr);
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check_modem_status(up);
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spin_unlock_irqrestore(&up->port.lock, flags);
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return IRQ_HANDLED;
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}
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spin_lock_irqsave(&up->port.lock, flags);
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iir = serial_in(up, UART_IIR);
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if (iir & UART_IIR_NO_INT) {
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spin_unlock_irqrestore(&up->port.lock, flags);
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@ -666,9 +623,9 @@ static irqreturn_t port_irq(int irq, void *dev_id)
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}
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lsr = serial_in(up, UART_LSR);
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if (lsr & UART_LSR_DR)
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receive_chars(up, &lsr);
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check_modem_status(up);
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/* lsr will be renewed during the receive_chars */
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if (lsr & UART_LSR_THRE)
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@ -701,7 +658,6 @@ static inline void dma_chan_irq(struct hsu_dma_chan *chan)
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/* Tx channel */
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if (chan->dirt == DMA_TO_DEVICE) {
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/* dma for irq should be done */
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chan_writel(chan, HSU_CH_CR, 0x0);
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up->dma_tx_on = 0;
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hsu_dma_tx(up);
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@ -851,7 +807,6 @@ static int serial_hsu_startup(struct uart_port *port)
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spin_unlock_irqrestore(&up->port.lock, flags);
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/* DMA init */
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/* When use DMA, TX/RX's FIFO and IRQ should be disabled */
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if (up->use_dma) {
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struct hsu_dma_buffer *dbuf;
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struct circ_buf *xmit = &port->state->xmit;
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@ -1090,11 +1045,9 @@ static int serial_hsu_request_port(struct uart_port *port)
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static void serial_hsu_config_port(struct uart_port *port, int flags)
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{
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#if 0
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struct uart_hsu_port *up =
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container_of(port, struct uart_hsu_port, port);
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up->port.type = PORT_MFD;
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#endif
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}
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static int
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@ -1426,7 +1379,7 @@ static void hsu_global_init(void)
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uport->port.ops = &serial_hsu_pops;
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uport->port.line = i;
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uport->port.flags = UPF_IOREMAP;
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/* make the maxim support rate to 2746800 bps */
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/* set the scalable maxim support rate to 2746800 bps */
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uport->port.uartclk = 115200 * 24 * 16;
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uport->running = 0;
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