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PCI: pciehp: Disable link notification across slot reset

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Disable the link notification (in addition to presence detect
notifications) across the slot reset since the reset could flap the link,
and we don't want to treat it as hot unplug followed by a hotplug.

Signed-off-by: Rajat Jain <rajatxjain@gmail.com>
Signed-off-by: Rajat Jain <rajatjain@juniper.net>
Signed-off-by: Guenter Roeck <groeck@juniper.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Rajat Jain 2014-02-04 18:30:40 -08:00 committed by Bjorn Helgaas
parent 02e93a8a7c
commit 06a8d89af5
1 changed files with 17 additions and 13 deletions
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24
drivers/pci/hotplug/pciehp_hpc.c
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@ -619,33 +619,37 @@ static void pcie_disable_notification(struct controller *ctrl)
/* /*
* pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
* bus reset of the bridge, but if the slot supports surprise removal we need * bus reset of the bridge, but if the slot supports surprise removal (or
* to disable presence detection around the bus reset and clear any spurious * link state change based hotplug), we need to disable presence detection
* (or link state notifications) around the bus reset and clear any spurious
* events after. * events after.
*/ */
int pciehp_reset_slot(struct slot *slot, int probe) int pciehp_reset_slot(struct slot *slot, int probe)
{ {
struct controller *ctrl = slot->ctrl; struct controller *ctrl = slot->ctrl;
struct pci_dev *pdev = ctrl_dev(ctrl); struct pci_dev *pdev = ctrl_dev(ctrl);
u16 stat_mask = 0, ctrl_mask = 0;
if (probe) if (probe)
return 0; return 0;
if (HP_SUPR_RM(ctrl)) { if (HP_SUPR_RM(ctrl) && !ATTN_BUTTN(ctrl)) {
pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE); ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
stat_mask |= PCI_EXP_SLTSTA_PDC;
}
ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
stat_mask |= PCI_EXP_SLTSTA_DLLSC;
pcie_write_cmd(ctrl, 0, ctrl_mask);
if (pciehp_poll_mode) if (pciehp_poll_mode)
del_timer_sync(&ctrl->poll_timer); del_timer_sync(&ctrl->poll_timer);
}
pci_reset_bridge_secondary_bus(ctrl->pcie->port); pci_reset_bridge_secondary_bus(ctrl->pcie->port);
if (HP_SUPR_RM(ctrl)) { pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
PCI_EXP_SLTSTA_PDC);
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE);
if (pciehp_poll_mode) if (pciehp_poll_mode)
int_poll_timeout(ctrl->poll_timer.data); int_poll_timeout(ctrl->poll_timer.data);
}
return 0; return 0;
} }