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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: Delay enabling hardware DBM feature
We enable hardware DBM bit in a capable CPU, very early in the boot via __cpu_setup. This doesn't give us a flexibility of optionally disable the feature, as the clearing the bit is a bit costly as the TLB can cache the settings. Instead, we delay enabling the feature until the CPU is brought up into the kernel. We use the feature capability mechanism to handle it. The hardware DBM is a non-conflicting feature. i.e, the kernel can safely run with a mix of CPUs with some using the feature and the others don't. So, it is safe for a late CPU to have this capability and enable it, even if the active CPUs don't. To get this handled properly by the infrastructure, we unconditionally set the capability and only enable it on CPUs which really have the feature. Also, we print the feature detection from the "matches" call back to make sure we don't mislead the user when none of the CPUs could use the feature. Cc: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Dave Martin <dave.martin@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -48,7 +48,8 @@
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#define ARM64_WORKAROUND_843419 27
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#define ARM64_HAS_CACHE_IDC 28
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#define ARM64_HAS_CACHE_DIC 29
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#define ARM64_HW_DBM 30
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#define ARM64_NCAPS 30
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#define ARM64_NCAPS 31
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#endif /* __ASM_CPUCAPS_H */
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@ -957,6 +957,57 @@ static int __init parse_kpti(char *str)
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__setup("kpti=", parse_kpti);
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#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
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#ifdef CONFIG_ARM64_HW_AFDBM
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static inline void __cpu_enable_hw_dbm(void)
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{
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u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
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write_sysreg(tcr, tcr_el1);
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isb();
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}
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static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
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{
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return has_cpuid_feature(cap, SCOPE_LOCAL_CPU);
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}
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static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
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{
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if (cpu_can_use_dbm(cap))
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__cpu_enable_hw_dbm();
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}
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static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
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int __unused)
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{
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static bool detected = false;
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/*
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* DBM is a non-conflicting feature. i.e, the kernel can safely
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* run a mix of CPUs with and without the feature. So, we
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* unconditionally enable the capability to allow any late CPU
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* to use the feature. We only enable the control bits on the
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* CPU, if it actually supports.
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*
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* We have to make sure we print the "feature" detection only
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* when at least one CPU actually uses it. So check if this CPU
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* can actually use it and print the message exactly once.
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*
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* This is safe as all CPUs (including secondary CPUs - due to the
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* LOCAL_CPU scope - and the hotplugged CPUs - via verification)
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* goes through the "matches" check exactly once. Also if a CPU
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* matches the criteria, it is guaranteed that the CPU will turn
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* the DBM on, as the capability is unconditionally enabled.
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*/
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if (!detected && cpu_can_use_dbm(cap)) {
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detected = true;
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pr_info("detected: Hardware dirty bit management\n");
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}
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return true;
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}
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#endif
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static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
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{
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/*
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@ -1133,6 +1184,26 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cache_dic,
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},
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#ifdef CONFIG_ARM64_HW_AFDBM
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{
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/*
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* Since we turn this on always, we don't want the user to
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* think that the feature is available when it may not be.
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* So hide the description.
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*
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* .desc = "Hardware pagetable Dirty Bit Management",
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*
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*/
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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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.capability = ARM64_HW_DBM,
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.sys_reg = SYS_ID_AA64MMFR1_EL1,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64MMFR1_HADBS_SHIFT,
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.min_field_value = 2,
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.matches = has_hw_dbm,
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.cpu_enable = cpu_enable_hw_dbm,
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},
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#endif
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{},
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};
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@ -448,16 +448,15 @@ ENTRY(__cpu_setup)
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tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
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#ifdef CONFIG_ARM64_HW_AFDBM
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/*
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* Hardware update of the Access and Dirty bits.
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* Enable hardware update of the Access Flags bit.
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* Hardware dirty bit management is enabled later,
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* via capabilities.
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*/
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mrs x9, ID_AA64MMFR1_EL1
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and x9, x9, #0xf
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cbz x9, 2f
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cmp x9, #2
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b.lt 1f
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orr x10, x10, #TCR_HD // hardware Dirty flag update
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1: orr x10, x10, #TCR_HA // hardware Access flag update
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2:
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cbz x9, 1f
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orr x10, x10, #TCR_HA // hardware Access flag update
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1:
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#endif /* CONFIG_ARM64_HW_AFDBM */
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msr tcr_el1, x10
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ret // return to head.S
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