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CRIS changes for 4.9

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Merge tag 'cris-for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris

Pull CRIS updates from Jesper Nilsson.

* tag 'cris-for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris:
  cris: return of class_create should be considered
  CRIS: defconfig: remove MTDRAM_ABS_POS
  CRIS v32: remove some double unlocks
  Fix typos
  cris: migrate exception table users off module.h and onto extable.h
  cris: v10: axisflashmap: remove unused ifdefs
  cris: use generic io.h
  cris: fix Kconfig mismatch when building with CONFIG_PCI
  cris: cardbus: fix header include path
  cris: add dev88_defconfig
  cris: irq: stop loop from accessing array out of bounds
  cris: fasttimer: fix mixed declarations and code compile warning
  cris: intmem: fix pointer comparison compile warning
  cris: intmem: fix device_initcall compile warning
This commit is contained in:
Linus Torvalds 2016-10-10 11:28:35 -07:00
commit 057a056ced
22 changed files with 83 additions and 217 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/cris/Kconfig
View File

@ -30,7 +30,7 @@ config GENERIC_CALIBRATE_DELAY
default y
config NO_IOPORT_MAP
def_bool y
def_bool y if !PCI
config FORCE_MAX_ZONEORDER
int

19
arch/cris/arch-v10/drivers/axisflashmap.c
View File

@ -177,15 +177,6 @@ static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
},
};
#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
/* Main flash device */
static struct mtd_partition main_partition = {
.name = "main",
.size = 0,
.offset = 0
};
#endif
/*
* Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
* chips in that order (because the amd_flash-driver is faster).
@ -369,16 +360,6 @@ static int __init init_axis_flash(void)
pidx++;
}
#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
if (mymtd) {
main_partition.size = mymtd->size;
err = mtd_device_register(mymtd, &main_partition, 1);
if (err)
panic("axisflashmap: Could not initialize "
"partition for whole main mtd device!\n");
}
#endif
if (mymtd) {
if (use_default_ptable) {
printk(KERN_INFO " Using default partition table.\n");

2
arch/cris/arch-v10/drivers/eeprom.c
View File

@ -395,7 +395,7 @@ static int eeprom_open(struct inode * inode, struct file * file)
static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig)
{
/*
* orig 0: position from begning of eeprom
* orig 0: position from beginning of eeprom
* orig 1: relative from current position
* orig 2: position from last eeprom address
*/

2
arch/cris/arch-v10/lib/dram_init.S
View File

@ -3,7 +3,7 @@
* This file is intended to be included from other assembler files
*
* Note: This file may not modify r9 because r9 is used to carry
* information from the decompresser to the kernel
* information from the decompressor to the kernel
*
* Copyright (C) 2000-2012 Axis Communications AB
*

2
arch/cris/arch-v32/drivers/cryptocop.c
View File

@ -1210,7 +1210,7 @@ static int cryptocop_setup_dma_list(struct cryptocop_operation *operation, struc
assert(active_count >= eop_needed_count);
assert((eop_needed_count == 0) || (eop_needed_count == 1));
if (eop_needed_count) {
/* This means that the bulk operation (cipeher/m2m) is terminated. */
/* This means that the bulk operation (cipher/m2m) is terminated. */
if (active_count > 1) {
/* Use zero length EOP descriptor. */
struct cryptocop_dma_desc *ed = alloc_cdesc(alloc_flag);

2
arch/cris/arch-v32/drivers/pci/bios.c
View File

@ -1,6 +1,6 @@
#include <linux/pci.h>
#include <linux/kernel.h>
#include <arch/hwregs/intr_vect.h>
#include <hwregs/intr_vect.h>
void pcibios_fixup_bus(struct pci_bus *b)
{

6
arch/cris/arch-v32/drivers/sync_serial.c
View File

@ -1627,6 +1627,12 @@ static int __init etrax_sync_serial_init(void)
/* Create a sysfs class for syncser */
syncser_class = class_create(THIS_MODULE, "syncser_class");
if (IS_ERR(syncser_class)) {
pr_err("Failed to create a sysfs class for syncser\n");
unregister_chrdev_region(syncser_first, minor_count);
cdev_del(syncser_cdev);
return -1;
}
/* Initialize Ports */
#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)

15
arch/cris/arch-v32/kernel/fasttimer.c
View File

@ -318,11 +318,13 @@ timer_trig_interrupt(int irq, void *dev_id)
static void timer_trig_handler(struct work_struct *work)
{
reg_timer_rw_ack_intr ack_intr = { 0 };
reg_timer_rw_intr_mask intr_mask;
reg_timer_rw_trig_cfg trig_cfg = { 0 };
struct fast_timer *t;
unsigned long flags;
reg_timer_rw_ack_intr ack_intr = { 0 };
reg_timer_rw_intr_mask intr_mask;
reg_timer_rw_trig_cfg trig_cfg = { 0 };
struct fast_timer *t;
fast_timer_function_type *f;
unsigned long d;
unsigned long flags;
/* We keep interrupts disabled not only when we modify the
* fast timer list, but any time we hold a reference to a
@ -350,9 +352,6 @@ static void timer_trig_handler(struct work_struct *work)
fast_timer_running = 0;
fast_timer_ints++;
fast_timer_function_type *f;
unsigned long d;
t = fast_timer_list;
while (t) {
struct fasttime_t tv;

3
arch/cris/arch-v32/kernel/irq.c
View File

@ -471,9 +471,8 @@ init_IRQ(void)
irq_set_default_host(domain);
of_node_put(np);
for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT; i++, j++) {
for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT && j < MACH_IRQS; i++, j++)
set_exception_vector(i, interrupt[j]);
}
/* Mark Timer and IPI IRQs as CPU local */
irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;

1
arch/cris/arch-v32/mach-a3/dma.c
View File

@ -41,7 +41,6 @@ int crisv32_request_dma(unsigned int dmanr, const char *device_id,
if (options & DMA_PANIC_ON_ERROR)
panic("request_dma error!");
spin_unlock_irqrestore(&dma_lock, flags);
return -EBUSY;
}
clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);

2
arch/cris/arch-v32/mach-a3/dram_init.S
View File

@ -3,7 +3,7 @@
* This file is intended to be included from other assembler files
*
* Note: This file may not modify r8 or r9 because they are used to
* carry information from the decompresser to the kernel
* carry information from the decompressor to the kernel
*
* Copyright (C) 2005-2007 Axis Communications AB
*

1
arch/cris/arch-v32/mach-fs/dma.c
View File

@ -43,7 +43,6 @@ int crisv32_request_dma(unsigned int dmanr, const char *device_id,
}
if (options & DMA_PANIC_ON_ERROR)
panic("request_dma error!");
spin_unlock_irqrestore(&dma_lock, flags);
return -EBUSY;
}
clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);

2
arch/cris/arch-v32/mach-fs/dram_init.S
View File

@ -3,7 +3,7 @@
* This file is intended to be included from other assembler files
*
* Note: This file may not modify r8 or r9 because they are used to
* carry information from the decompresser to the kernel
* carry information from the decompressor to the kernel
*
* Copyright (C) 2000-2007 Axis Communications AB
*

13
arch/cris/arch-v32/mm/intmem.c
View File

@ -113,14 +113,14 @@ void crisv32_intmem_free(void* addr)
allocation->status = STATUS_FREE;
/* Join with prev and/or next if also free */
if ((prev != &intmem_allocations) &&
if ((&prev->entry != &intmem_allocations) &&
(prev->status == STATUS_FREE)) {
prev->size += allocation->size;
list_del(&allocation->entry);
kfree(allocation);
allocation = prev;
}
if ((next != &intmem_allocations) &&
if ((&next->entry != &intmem_allocations) &&
(next->status == STATUS_FREE)) {
allocation->size += next->size;
list_del(&next->entry);
@ -145,5 +145,12 @@ unsigned long crisv32_intmem_virt_to_phys(void* addr)
(unsigned long)intmem_virtual + MEM_INTMEM_START +
RESERVED_SIZE);
}
device_initcall(crisv32_intmem_init);
static int __init crisv32_intmem_setup(void)
{
crisv32_intmem_init();
return 0;
}
device_initcall(crisv32_intmem_setup);

1
arch/cris/configs/artpec_3_defconfig
View File

@ -25,7 +25,6 @@ CONFIG_MTD_RAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
# CONFIG_INPUT is not set

48
arch/cris/configs/dev88_defconfig Normal file
View File

@ -0,0 +1,48 @@
CONFIG_BUILTIN_DTB="dev88"
# CONFIG_SWAP is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ETRAX_FAST_TIMER=y
CONFIG_ETRAXFS=y
CONFIG_ETRAX_DRAM_SIZE=32
CONFIG_ETRAX_FLASH1_SIZE=4
CONFIG_ETRAX_MEM_GRP1_CONFIG=0x40688
CONFIG_ETRAX_MEM_GRP3_CONFIG=0x3
CONFIG_ETRAX_MEM_GRP4_CONFIG=0x10040
CONFIG_ETRAX_SDRAM_GRP0_CONFIG=0x958
CONFIG_ETRAX_SDRAM_TIMING=0x824a
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_ETRAX_ETHERNET=y
CONFIG_ETRAX_AXISFLASHMAP=y
CONFIG_DEVTMPFS=y
CONFIG_MTD_RAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
# CONFIG_INPUT is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_VT is not set
CONFIG_SERIAL_ETRAXFS=y
CONFIG_SERIAL_ETRAXFS_CONSOLE=y
CONFIG_GPIO_ETRAXFS=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y

1
arch/cris/configs/etrax-100lx_v2_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_MTD_RAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
# CONFIG_INPUT is not set

1
arch/cris/configs/etraxfs_defconfig
View File

@ -25,7 +25,6 @@ CONFIG_MTD_RAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
# CONFIG_INPUT is not set

2
arch/cris/include/arch-v32/arch/cryptocop.h
View File

@ -81,7 +81,7 @@ struct cryptocop_tfrm_cfg {
unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
/* CBC initialisation vector for cihers. */
/* CBC initialisation vector for ciphers. */
u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
/* The position in output where to write the transform output. The order

171
arch/cris/include/asm/io.h
View File

@ -8,34 +8,6 @@
#include <asm-generic/iomap.h>
#include <linux/kernel.h>
struct cris_io_operations
{
u32 (*read_mem)(void *addr, int size);
void (*write_mem)(u32 val, int size, void *addr);
u32 (*read_io)(u32 port, void *addr, int size, int count);
void (*write_io)(u32 port, void *addr, int size, int count);
};
#ifdef CONFIG_PCI
extern struct cris_io_operations *cris_iops;
#else
#define cris_iops ((struct cris_io_operations*)NULL)
#endif
/*
* Change virtual addresses to physical addresses and vv.
*/
static inline unsigned long virt_to_phys(volatile void * address)
{
return __pa(address);
}
static inline void * phys_to_virt(unsigned long address)
{
return __va(address);
}
extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
@ -48,147 +20,6 @@ extern void iounmap(volatile void * __iomem addr);
extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the CRIS architecture, we just read/write the
* memory location directly.
*/
#ifdef CONFIG_PCI
#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
#else
#define PCI_SPACE(x) 0
#endif
static inline unsigned char readb(const volatile void __iomem *addr)
{
if (PCI_SPACE(addr) && cris_iops)
return cris_iops->read_mem((void*)addr, 1);
else
return *(volatile unsigned char __force *) addr;
}
static inline unsigned short readw(const volatile void __iomem *addr)
{
if (PCI_SPACE(addr) && cris_iops)
return cris_iops->read_mem((void*)addr, 2);
else
return *(volatile unsigned short __force *) addr;
}
static inline unsigned int readl(const volatile void __iomem *addr)
{
if (PCI_SPACE(addr) && cris_iops)
return cris_iops->read_mem((void*)addr, 4);
else
return *(volatile unsigned int __force *) addr;
}
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
static inline void writeb(unsigned char b, volatile void __iomem *addr)
{
if (PCI_SPACE(addr) && cris_iops)
cris_iops->write_mem(b, 1, (void*)addr);
else
*(volatile unsigned char __force *) addr = b;
}
static inline void writew(unsigned short b, volatile void __iomem *addr)
{
if (PCI_SPACE(addr) && cris_iops)
cris_iops->write_mem(b, 2, (void*)addr);
else
*(volatile unsigned short __force *) addr = b;
}
static inline void writel(unsigned int b, volatile void __iomem *addr)
{
if (PCI_SPACE(addr) && cris_iops)
cris_iops->write_mem(b, 4, (void*)addr);
else
*(volatile unsigned int __force *) addr = b;
}
#define writeb_relaxed(b, addr) writeb(b, addr)
#define writew_relaxed(b, addr) writew(b, addr)
#define writel_relaxed(b, addr) writel(b, addr)
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
#define mmiowb()
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
/* I/O port access. Normally there is no I/O space on CRIS but when
* Cardbus/PCI is enabled the request is passed through the bridge.
*/
#define IO_SPACE_LIMIT 0xffff
#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
static inline void outb(unsigned char data, unsigned int port)
{
if (cris_iops)
cris_iops->write_io(port, (void *) &data, 1, 1);
}
static inline void outw(unsigned short data, unsigned int port)
{
if (cris_iops)
cris_iops->write_io(port, (void *) &data, 2, 1);
}
static inline void outl(unsigned int data, unsigned int port)
{
if (cris_iops)
cris_iops->write_io(port, (void *) &data, 4, 1);
}
static inline void outsb(unsigned int port, const void *addr,
unsigned long count)
{
if (cris_iops)
cris_iops->write_io(port, (void *)addr, 1, count);
}
static inline void outsw(unsigned int port, const void *addr,
unsigned long count)
{
if (cris_iops)
cris_iops->write_io(port, (void *)addr, 2, count);
}
static inline void outsl(unsigned int port, const void *addr,
unsigned long count)
{
if (cris_iops)
cris_iops->write_io(port, (void *)addr, 4, count);
}
#define inb_p(port) inb(port)
#define inw_p(port) inw(port)
#define inl_p(port) inl(port)
#define outb_p(val, port) outb((val), (port))
#define outw_p(val, port) outw((val), (port))
#define outl_p(val, port) outl((val), (port))
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
#include <asm-generic/io.h>
#endif

2
arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h
View File

@ -61,7 +61,7 @@
#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_)
#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH)
/*--- Obsolete. Kept for backw compatibility. ---*/
/*--- Obsolete. Kept for backward compatibility. ---*/
/* Reads (or writes) a byte/uword/udword from the specified mode
register. */
#define IO_RD(reg) (*(volatile u32*)(reg))

2
arch/cris/mm/fault.c
View File

@ -6,7 +6,7 @@
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/extable.h>
#include <linux/wait.h>
#include <linux/uaccess.h>
#include <arch/system.h>